Abstract: Capacitors for integrated circuits with a common polysilicon layer for both MOS gates (274, 276, 278) and capacitor (270) lower plates but with implanted doping for the gates and masked diffusive doping for the capacitor plates.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: Contacts for an electronic device are formed by providing a substrate (12) that has at least two access line structures (16) for a memory array (14) and a periphery structure (20) for a peripheral circuit (18) to the memory array (14). A first insulative layer (40) is formed outwardly of the substrate (12), the access line structures (16), and the periphery structure (20). A contact area of the periphery structure (20) is exposed through the first insulative layer (40) while maintaining the first insulative layer (40) over at least a contact overlap portion (48) of the access line structures (16). A second insulative layer (60) is formed outwardly of the substrate (12), the access line structures (16), the periphery structure (20), and the first insulative layer (40).

Abstract: A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS devices and the device, primarily for a polyphase bridge circuit. For the low side device, a substrate of a first conductivity type is provided having a first buried layer of opposite conductivity type thereon. A second buried layer of the first conductivity type is formed over the first buried layer and a further layer of the first conductivity type is formed over the second buried layer. A sinker extending through the further layer to the first buried layer is formed to isolate the second buried layer and the further layer from the substrate. Formation of an MOS device in the further layer including source, drain and gate regions is completed and the sinker is connected to a source terminal of the device.

Abstract: An array of bolometers suspended over a substrate by support arms located beneath the corresponding bolometer to allow maximum fill factor in the array.

Abstract: A method of encapsulating metal lines (130, 132, 134, 136, 138) by implantation of dopants to form surface regions (131, 133, 135, 137, 139) after the metal lines have been fabricated. The surface regions may act as passivation layers and electromigration inhibitors and so forth.

Abstract: Video compression coding with partitioning of data into motion vector data and texture data with reversible Golomb-Rice type codes for the data. Resynchronization markers separate the data types, and the reversible coding permits decoding in both forward and backward directions to minimize data discarded due to errors.

Abstract: A silicide process using a pre-anneal amorphization implant prior to silicide anneal. A layer of titanium is deposited and reacted to form titanium silicide (32) and titanium nitride. The titanium nitride is removed and a pre-anneal amorphization implant is performed to enable increased transformation of the silicide (32) from a higher resistivity phase to a lower resistivity phase. A heavy dopant species (40) is used for the pre-anneal amorphization implant such as arsenic, antimony, or germanium. After the implant, the silicide anneal is performed to accomplish the transformation. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.

Abstract: This invention is to a method for producing a uniform nitrogen doped layer in silicon that effectively reduces boron transient enhanced diffusion (TED) for ultra shallow junction formation. A silicon substrate (10) from an n-type single crystal silicon grown in the [100] direction and cut into wafers with (100) faces exposed is pre-amorphized by silicon and germanium implantation (11). Nitrogen is implanted to a depth of 0.7 &mgr;m through the amorphous layer with multiple implantations at energies ranging from 10 keV to 250 keV (12). Boron is implanted into the pre-amorphized and nitrogen contained silicon substrate (13). After boron implantation, the substrate is subjected to a rapid thermal anneal process to remove lattice damage and activate boron. The resulting nitrogen and boron profiles (14) in the substrate of this invention exhibit suppressed boron TED and enable formation of p+ ultra shallow junctions.

Abstract: Chemical mechanical polishing slurry with functionalized silica abrasive particles, the functionalization permits high pH slurry without rapid degradation of silica particles and also permits the modification of surface properties of abrasive particles to modify slurry behavior. One example of modified behavior would be to enhance selectivity by controlling particle interaction with different surfaces on the wafer.

Abstract: A capacitor dielectric with multiple layers of differing high dielectric constant materials such as SrTiO3 and BaSrTiO3 in which an inner layer has a higher dielectric constant but also higher leakage current than outer layers on each side of the inner layer which have lower leakage currents but also lower dielectric constants.

Abstract: An FeRAM in which sensing occurs without a dummy cell, using an unselected bitline as a reference. The read cycle includes two opposed pulses on the drive line: the first pulse provides a data-dependent signal out of the selected cell, and the second pulse restores the bit line to a level such that the DC bias voltage on an unselected bitline provides an optimal reference.

Abstract: A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: In one embodiment, the present invention provides a method of forming a dynamic random access memory device which utilizes self-aligned contact pads 40a and 40b for the bit line and storage node contacts. A transfer gate 14 is formed at the fact of a semiconductor region 30. The semiconductor 30 includes a bit line contact region 44 and storage node contact region adjacent opposite edges of the transfer gate 14. Transfer gate 14 is surrounded with an insulating material 34/38. A conductive layer 40 is formed over the transfer gate 14, over the bit line contact region 44 and over the storage node contact region. This conductive layer 40 is then etched so that a first portion 40a of the conductive layer 40 provides an electrical contact to the bit line contact region 44 and a second portion 40b of the conductive layer 40 provides an electrical contact to the storage node contact region.

Abstract: A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 M Pa, and preferably no more than about 30 M Pa, at temperatures ranging from about 100°-300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: An enlarged contact area (62, 162) is formed for a gate structure (14, 114) by providing a substrate (12, 112) having at least one gate electrode (22, 122) thereon. An implant sidewall (42, 142) is formed outwardly from the gate electrode (22, 122) and defines an implant area (44, 144) in the substrate (12, 112). A terminal (50, 150) is formed for the gate electrode (22, 122) by implanting dopants (46, 146) into the implant area (44, 144) in the substrate (12, 112). The implant sidewall (42, 142) is removed and an insulative sidewall (60, 160) is formed outwardly from the gate electrode (22, 122). The insulative sidewall (60, 160) has a thickness less than that of the implant sidewall (42, 142) to define an enlarged contact area (62, 162) for the terminal (50, 150).

Abstract: A method of making connection between an aluminum or aluminum based material and tungsten. The method includes providing an underlying region containing a layer of tungsten thereover. The underlying region is preferably a layer of titanium over which is a layer of titanium nitride. The layer of tungsten is etched back to the underlying region while exposed tungsten is retained over a portion of the underlying region. The underlying region also may contain a via therein which contains the exposed tungsten. An nitrogen-containing plasma, preferably elemental nitrogen, is then applied to the exposed tungsten and exposed underlying region and a layer of a barrier material is formed by reaction of the nitrogen in the plasma and the tungsten over the exposed tungsten. A further barrier layer, preferably titanium nitride, is optionally then applied followed by a layer of aluminum over the exposed surface, the barrier layer isolating the layer of aluminum from the tungsten.