Abstract: An efficient decoding of reversible variable length codes of the type implemented for H.263++ and MPEG-4 DCT coefficients using lookup tables. Simple-profile MPEG-4 also has the option of using reversible variable length codewords (RVLC) that can be decoded in either the forward or backward direction, for error recovery. Because of the special structure of RVLC codewords, the decoding techniques for regular VLC are less efficient with RVLC. A new method for RVLC decoding is described.

Abstract: Device and method of EEPR4 post processing in an EPR4 detection system to remove single bit errors by applying 1+D to the samples and comparing this to (1−D)(1+D)3 to the detected EPR4 bits.

Abstract: A photocell for detecting light includes at least two tiers or structures, one disposed over the other, each tier having a metal-insulator-semiconductor (M-I-S) or a semiconductor-insulator-metal (S-I-M) structure. Each M-I-S structure includes a semiconductor diffusion layer capable of developing a depletion region, a thin insulator layer disposed on the diffusion layer, and a contact layer disposed on the thin insulator layer. Each S-I-M structure includes a contact layer, a thin insulator layer disposed on the contact layer, and a semiconductor diffusion layer disposed on the thin insulator layer, the semiconductor layer capable of developing a depletion region. When light is incident on each depletion region, a current indicative of the light detected in each depletion region flows through the respective contact layer. Also provided is a semiconductor-insulator-metal (S-I-M) structure that detects light. Two- and three-tiered photocells made of M-I-S and/or S-I-M structures are also provided.

Abstract: An inlaid interconnect fabrication method using a silicon carbide polish stop layer for protection of mechanically weak dielectric such as porous silicon dioxide (xerogel) during chemical mechanical polishing.

Abstract: An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

Abstract: In one form of the invention, a process of sending real-time information from a sender computer to a receiver computer coupled to the sender computer by a packet network wherein packets sometimes become lost, includes steps of directing packets containing the real-time information from the sender computer by at least one path in the packet network to the receiver computer, and directing packets containing information dependent on the real-time information from the sender computer by at least one path deversity path in the packet network to the same receiver computer.

Abstract: A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.

Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.

Abstract: A power supply (500) with vertical field effect transistor synchronous rectifiers (VFET1 and VFET2) having drivers (VFET Driver1 and VFET Driver2) which provide bipolar mode of operation by diode clamping an inductor overshoot which forwards biases the gate-source junction. The rectifiers have low on resistance useful in low output voltage power supplies.

Abstract: A combinatorial polynomial multiplier for Galois Field 256 arithmetic utilizes fewer components than an iterative Galois Field 256 arithmetic multiplier and operates 8 times faster. The combinatorial multiplier employs AND and XOR functions and operates in a single clock cycle. It can reduce the number of transistors required for the Galois Field 256 arithmetic multiplier for a Reed-Solomon decoder by almost 90%.

Abstract: A process of removing fluorine from a chemical deposition reactor includes the step of injecting a gaseous mixture of nitrogen and hydrogen into the reactor, the volume ratio of nitrogen to hydrogen in the gaseous mixture being in the range of from 1:1 to 6:1. More preferably the N2/H2 ratio is in the range of 2.5 to 4.5:1. The gaseous mixture is ionized with a RF induced energy discharge, with a RF power setting typically in the range of from 200 to 250 watts at an RF frequency of 13.5 MHZ. The gaseous mixture is injected into the reactor for a predetermined period of time based upon the thickness of a material, typically a metal such as tungsten, deposited upon a wafer in the reactor during a semiconductor fabrication process.

Abstract: An analyzer and synthesizer (500) for human speech using LPC filtering (530) of an excitation of mixed (508-518-520) voiced pulse train (502) and unvoiced noise (512) with fractional sampling period pitch period determination.

Abstract: A capacitor (100) with a high dielectric constant oxide dielectric (102) plus Ir- or Ir and Rh bond over the oxygen site in Barium strontium titanate (BST) dielectric to achieve the high Schottky barrier, and very thin layers of Ir or Rh with conductive oxide backing layers (106, 116) provide oxygen depletion deterrence. Rh-containing capacitor plates (104, 114) yielding high Schottky barrier interfaces.

Abstract: A self-aligned silicide process with a selective etch of unreacted metal (plus any nitride) with respect to silicide plus a two step process of highly selective strip of unreacted metal (plus any nitride) followed by a silicide etch to remove unwanted silicide filament.

Abstract: A method of image encoding using subband decomposition followed by plus zerotree coding with a symbol replacement for significant coefficients.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A Viterbi type decoder which discards paths with metrics more than a distance from the smallest metric with the distance determined by the smallest distance between paths in the trellis.

Abstract: A method for simultaneously producing areas of paraelectric states and areas of ferroelectric states on a single thin film layer, thereby reducing the number of processing steps required to produce integrated chips containing both standard capacitors and non-volatile memory devices from the number of steps needed using the conventional approach. A device containing both ferroelectric capacitors and non-ferroelectric capacitors using a single thin film as the dielectric.

Abstract: A semiconductor processing tool evaluation and design method which replaces tool specifications with a requirements region plus associated evaluation functions for iterative feedback tool design.