Abstract: A flip-flop circuit that includes a set of three p-channel connectors connected in parallel between a supply voltage (Vdd) and a first control node. The circuit further includes three n-channel transistors connected in series between the first control node and Vss. The first control node controls the gate of a p-channel transistor connected between Vdd and an output node. A set of n-channel transistors is connected between the output node and ground. The gates of these transistors are controlled by the clock signal, a delayed clock signal, and an inverted copy of the data signal, which is provided, via a control inverter, to a second control node. The first control node drives the output node to a first state and the second control node drives the output node to a second state. The first and second control nodes are preferably decoupled.

Abstract: A configuration database associated with a hardware system stores at least one data structure defining a Dial instance and a mapping between each of a plurality of possible input values of the Dial instance and a respective one of a corresponding plurality of output values, where the plurality of output values controls which of a plurality of different possible latch values is placed in a hardware latch to configure the hardware system. The configuration database further indicates an association between the Dial instance and the hardware latch. In response to receipt of a request specifying an input value for the Dial instance, the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value is obtained based upon the output value and the association. The latch value is then provided to the hardware system to set the hardware latch to the desired latch value.

Abstract: A symmetric multiprocessor data processing system having an apparatus for imprecisely tracking cache line inclusivity of a higher level cache is disclosed. The symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units is associated with a level one cache memory. All the level one cache memories are associated with an imprecisely inclusive level two cache memory. The imprecisely inclusive level two cache memory includes a tracking means for imprecisely tracking cache line inclusivity of the level one cache memories. The tracking means includes a last_processor_to_store field and a more_than_two_loads field per cache line. When the more_than_two_loads field is asserted, except for a specific cache line in the level one cache memory associated with the processor indicated in the last_processor_to_store field, all cache lines within the level one cache memories that shared identical information with that specific cache line are invalidated.

Abstract: A method, computer program product, and distributed data processing system for lazy deregistration of memory regions. Specifically, the present invention is directed to memory regions that are written to and from by an Integrated Protocol Suite Offload Engine (IPSOE) in accordance with a preferred embodiment of the present invention. A mechanism is provided for lazy deregistration of memory regions once the region is no longer required for a specific data transfer being carried out by the IPSOE. Rather than deregistering a memory region after a data transfer has been carried out, the memory region remains registered for some selected period of time. After that selected period of time passes, the region is then deregistered. If a second data transfer using this memory region occurs while the memory region is still registered, the registration overhead is avoided for this second data transfer.

Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.

Abstract: A method and system for determining liveness of targets within a metaserver environment utilizing programmable network interfaces. The network interface has access to the associated target computer's processor and memory. A memory location on the target is allocated to storing an internal liveness parameter. The parameter increases when the computer system is making forward progress or operating. The MetaServer stores an initial parameter value of the target when it activates the target. After a pre-selected period, the network interface of the target accesses the associated memory location and provides the current value of the parameter to the MetaServer. When the now value is larger than the previously stored value, the target is assumed to be live.

Abstract: A high speed static multiplexer comprising: (1) a plurality of data inputs and at least one select input; (2) an output; (3) a high voltage rail and a low voltage rail; (4) a pull-up circuit coupled between the output and the high voltage rail and further coupled to receive the data inputs and the select input so that the pull-up circuit generates a first logic state at the output in response to the selected data input having that first logic state; (5) and a pull-down circuit coupled between the output and the low voltage rail and further coupled to receive the data inputs and the select input, so that the pull-down circuit generates a second logic state at the output in response to the selected data input having that second logic state.

Abstract: A scanning heat flow probe for making quantitative measurements of heat flow through a device under test is provided. In one embodiment the scanning heat flow probe includes an electric current conductor in a cantilever beam connected to a probe tip and coupled to two voltmeter leads. The probe also includes two thermocouple junctions in the cantilever beam electrically isolated from the electric current conductor and the two voltmeter leads. Heat flow is derived quantitatively using only voltage and current measurements. In other forms, the invention relates to the calibration of scanning heat flow probes through a method involving interconnected probes, and relates to the minimization of heat flow measurement uncertainty by probe structure design practices.

Abstract: A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time.

Abstract: A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, creating error signals for each of the multiphase clock signals using the data stream, selecting at least one of the error signals based on retime state signals, correcting the multiphase clock signals using the error signal to produce corrected multiphase clock signals, and sampling the data stream using one of the corrected multiphase signals to produce a retimed data signal. The multiphase clock signals may be subharmonics of the data stream. In one embodiment, an UP error signal and a DN error signal are created for each of the multiphase clock signals, wherein the selecting step selects one of the UP error signals and one of the DN error signals, and the selected UP error signal and the selected DN error signal are applied to inputs of a charge pump to correct the clock signals. A multiphase voltage-controlled oscillator may be used to provide the multiphase clock signals.

Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Abstract: A set of local invalidation buses for a highly scalable shared cache memory hierarchy is disclosed. A symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units is associated with a level one cache memory. All the level one cache memories are associated with an imprecisely inclusive level two cache memory. In addition, a group of local invalidation buses is connected between all the level one cache memories and the level two cache memory. The imprecisely inclusive level two cache memory includes a tracking means for imprecisely tracking cache line inclusivity of the level one cache memories. Thus, the level two cache memory does not have dedicated inclusivity bits for tracking the cache line inclusivity of each of the associated level one cache memories. The tracking means includes a last_processor_to_store field and a more_than_two_loads field per cache line.

Abstract: A voltage controlled oscillator (VCO) is constructed using a series ring connection of an odd number K of logic inverters where K is greater than three. Each sequence of three of the logic inverters has voltage controlled feed-forward conduction circuit coupled in parallel. Each of the feed-forward circuits has the same phase between its input and output as the path it parallels. The control voltage of the feed-forward circuits operates to decrease the path delay of the logic inverters when they are conducting. Selectable inverters are connected in parallel with each logic inverter using a P and an N channel field effect transistor (FET). The N channel FET is controlled with a Mode signal and the P channel FET is controlled by a Modeb signal which is generated by inverting the Mode signal. The Mode and Modeb signals control the connection of the selectable inverters are in parallel with the logic inverters thus increasing the drive capability of the parallel combination of inverters.

Abstract: Physical design optimizations for integrated circuits, such as placement, buffer insertion, floorplanning and routing, require fast and accurate analysis of resistive-capacitive (RC) delays in the network. A method is disclosed for estimating delays at nodes in an RC circuit by calculating a first and second impulse response moments of the RC circuit, and matching the impulse response moments to a Weibull distribution. Based on the match, a signal delay value is computed. The invention may thus be used to determine whether the RC circuit meets a desired optimization condition, based on the signal delay value. In the exemplary implementation, the signal delay value at a delay point is calculated by finding a percentile of the Weibull distribution corresponding to the delay point. This implementation is accurate and very efficient as it uses only two very small look-up tables.

Abstract: An installation apparatus and method for actuating the electrical connection of a land grid array module to a printed wiring board is provided. A backside stiffener with load posts is attached to a printed wiring board. A load plate, module, plurality of load columns, and springplate are operably connected to the load posts. An actuation screw operably connected to the springplate is rotated imparting an actuation force to the module. The backside stiffener includes a local stiffener, wherein the local stiffener causes a deflection in the printed wiring board complementary to the deflection of the module when the actuation force is applied.

Abstract: A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided a set of directional bits in addition to the coherency state bits and the address tag. The directional bits provide information that includes a processor cache identification (ID) and routing method. The processor cache ID indicates which processor's operation resulted in the cache line of the local processor changing to the invalidate (I) coherency state. The routing method indicates what transmission method to utilize to forward the cache line, from among a local system bus or a switch or broadcast mechanism. Processor/Cache directory logic provide responses to requests depending on the values of the directional bits.

Abstract: A trace array for recording states of signals includes N-storage locations for k trace signals. In the write mode, an address generator combines the outputs of an event signal counter and a cycle clock counter to generate trace array addresses. A start code is written each time an event signal occurs and event addresses are saved. Recording is stopped by a stop signal and the stop address is saved. A compression code and time stamp code are written when no state changes occur in any trace signals at the cycle clock times to compress recorded trace signal data. An output processor reads out stored states of the trace signals and uses the start codes, event addresses, stop address, compression code and time stamp to reconstruct the original trace signal sequences for analysis.

Abstract: According to an apparatus form of the invention, integrated circuitry on a single chip includes a bit-programmable voltage regulator supplying voltage to first circuitry on the chip. The integrated circuitry also includes second circuitry operable for characterizing performance of the first circuitry. Control circuitry on the chip is operable, responsive to the characterizing performed by the second circuitry, to output at least one digital control bit for controlling the regulator output voltage supplying the first circuitry. In another aspect, the integrated circuitry is operable to receive an externally generated, time-based reference signal, and the second circuitry includes an on-chip oscillator for generating a performance characterizing signal. The performance characterizing signal varies in frequency in correspondence with the performance of the first circuitry.

Abstract: Initially, a SMI trap detects an application accessing a memory location associated with a physical hardware device. The SMI trap receives the device address for the address bus and compares that address with memory addresses for hardware devices being virtualized by virtual device simulators. If the address matches an available virtual device, the SMI caches the address, hooks and caches the corresponding IO instruction for the memory address and issues a SMI. A SMI handler receives the SMI and determines which virtual device simulator to call. Once activated by the SMI handler, the virtual device simulator interacts with the application and then returns control to the processor.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.