Abstract: A cache controller for a processor in a remote node of a system bus in a multiway multiprocessor link sends out a cache deallocate address transaction (CDAT) for a given cache line when that cache line is flushed and information from memory in a home node is no longer deemed valid for that cache line of that remote node processor. A local snoop of that CDAT transaction is then performed as a background function by other processors in the same remote node. If the snoop results indicate that same information is valid in another cache, and that cache decides it better to keep it valid in that remote node, then the information remains there. If the snoop results indicate that the information is not valid among caches in that remote node, or will be flushed due to the CDAT, the system memory directory in the home node of the multiprocessor link is notified and changes state in response to this.

Abstract: In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access, snoop operation, and system controller hint information for the corresponding cache line. Each entry includes different subentries for different processors which have accessed the corresponding cache line, with subentries containing a processor access sequence segment, a snoop operation sequence segment, and a system controller hint history segment. In addition to an address tag, within each system controller bus transaction sequence log directory entry is contained one or more opcodes identifying bus operations addressing the corresponding cache line, a processor identifier associated with each opcode, and a timestamp associated with each opcode.

Abstract: A method of executing test cases with a parallel test segment of a test sequence, is disclosed. Initially, a test sequence is defined that includes a parallel test segment including at least a first test case and a second test case. A cycle time of the parallel test segment is determined where the determined cycle time is greater than the execution time of either the first or second test cases. The test sequence is then executed repeatedly. During each execution of the test sequence, the start point of the first and second test cases within the parallel test segment are varied with respect to one another preferably in a random fashion.

Abstract: A bus having improved performance over prior art busses is provided. In one embodiment, the bus includes a first wire having a plurality of intervals, a second wire having a plurality of intervals, and a third wire having a plurality of intervals. The first, second, and third wires are intertwined with each other. Some intervals of the wires include a buffer and some other intervals of the wires include an inverter. In some embodiments, the intervals of the wires that include the buffer are middle wires and in other embodiments, the intervals of the wires the include the buffer are outer wires.

Abstract: A level shifter having a data input node, a first inverter having its input connected to the data input node, a second inverter connected to an output of the first inverter, a data output node, a latch having its output connected to the data output node, a first NFET connected between an input of the latch and a ground potential, and having its gate electrode connected to an output of the second inverter, and a second NFET connected between the data output node and the ground potential, and having its gate electrode connected to the output of the first inverter. The level shifter provides for a conversion of a data signal from a power supply domain of 1.8 volts to one of 3.3 volts.

Abstract: A method for forming a thermoelement for a thermoelectric cooler is provided. In one embodiment a first substrate having a plurality of pointed tips separated by valleys wherein the substrate is covered by a metallic layer, portions of the metallic layer is covered by an insulator, and other portions of the metallic layer are exposed is formed. The other portions of the metallic layer that are exposed are covered with a thermoelectric material overcoat. A second substrate of thermoelectric material is then fused to the pointed tip side of the first substrate by, for example, heating the back of the first substrate to melt the thermoelectric material overcoat or by passing current through the pointed tips to induce Joule heating and thereby melt the thermoelectric material overcoat.

Abstract: According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a “ring”) includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagation delay of m and the N inverters have signal propagation delay of n. The circuitry also includes means for selecting whether to exclude the N inverters from operating in the loop operable for receiving a select signal on a data input. The selecting means times assertion of the select signal on an output to select the number of inverters. In order to glitchlessly change the number of inverters operating in the loop, the selecting means has a certain delay greater than delay n.

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0's on their drive interfaces, and setting all receive interfaces on the chips to receive 0's and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0's, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking 1 test is then repeated for any additional interfaces that require testing.

Abstract: A method for accelerating input/output operations within a data processing system is disclosed. Initially, a determination is initially made in a cache controller as to whether or not a bus operation is a data transfer from a first memory to a second memory without intervening communications through a processor, such as a direct memory access (DMA) transfer. If the bus operation is such data transfer, a determination is made in a cache memory as to whether or not the cache memory includes a copy of data from the data transfer. If the cache memory does not include a copy of data from the data transfer, a cache line is allocated within the cache memory to store a copy of data from the data transfer.

Abstract: A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node including a home system memory. The remote node includes a plurality of snoopers coupled to a local interconnect. The plurality of snoopers includes a cache that caches a cache line corresponding to but modified with respect to data resident in the home system memory. The cache has a cache controller that issues a deallocate operation on the local interconnect in response to deallocating the modified cache line. The remote node further includes a node controller, coupled between the local interconnect and the node interconnect, that transmits the deallocate operation to the home node with an indication of whether or not a copy of the cache line remains in the remote node following the deallocation. In this manner, the local memory directory associated with the home system memory can be updated to precisely reflect which nodes hold a copy of the cache line.

Abstract: The packaging architecture for a multiple array transceiver using a flexible cable of the present invention provides a 90-degree transition between an optical signal input at a communications chassis bulkhead and an interior board within the communications chassis. The packaging architecture system comprises a forward vertical carrier having an optical converter, a paddle card, a flexible cable operably connected between the forward vertical carrier and the paddle card, and a rearward horizontal I/O block operably connected to the paddle card, the rearward horizontal I/O block oriented about 90 degrees from the forward vertical carrier. The multiple array transceiver makes the 90-degree transition within a narrow gap established by industry and manufacturer standards. The multiple array transceiver further provides cooling through a heat sink.

Abstract: A pipelined processor and method are disclosed for speculatively determining dependencies. The processor processes a plurality of instructions in order. A speculative detection circuit which takes multiple clock cycles to operate determines whether a dependency exists. The speculative detection circuit inserts a single-cycle pipeline stall only in response to a determination that a speculative dependency exists.

Abstract: A selectable interface for interfacing integrated circuit modules is disclosed. The bus interface for interconnecting a first circuit module and a second circuit module includes a transmitter pair located within the first circuit module and a receiver pair located within the second circuit module. The transmitter pair, which can be selectable between a differential mode and a single-ended mode, transmits data from the first circuit module to the second circuit module. The receiver pair, which can also be selectable between a differential mode and a single-ended mode, receives data from the transmitter pair.

Abstract: A method for increasing performance optimization in a multiprocessor data processing system. A number of predetermined thresholds are provided within a system controller logic and utilized to trigger specific bandwidth utilization responses. Both an address bus and data bus bandwidth utilization are monitored. Responsive to a fall of a percentage of data bus bandwidth utilization below a first predetermined threshold value, the system controller provides a particular response to a request for a cache line at a snooping processor having the cache line, where the response indicates to a requesting processor that the cache line will be provided. Conversely, if the percentage of data bus bandwidth utilization rises above a second predetermined threshold value, the system controller provides a next response to the request that indicates to any requesting processors that the requesting processor should utilize super-coherent data which is currently within its local cache.

Abstract: System bus snoopers within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the dynamic application sequence behavior information for the target cache line to their snoop responses. The system controller, which may also maintain dynamic application sequence behavior information in a history directory, employs the available dynamic application sequence behavior information to append “hints” to the combined response, appends the concatenated dynamic application sequence behavior information to the combined response, or both. Either the hints or the dynamic application sequence behavior information may be employed by the bus master and other snoopers in cache management.

Abstract: A method for allocating memory in a data processing system in which a configuration table indicative of the system's physical memory is generated following a boot event. The configuration table is then modified to identify a portion of the system's physical memory thereby hiding the remaining portion from the operating system. Subsequently, a memory allocation request is initiated by an application program. A device driver invoked by the application program then maps physical memory from the hidden portion to the application's virtual address space to satisfy the application request. The application program may be executing on a first node of a multi-node system in which each node is associated with its own local memory, In this embodiment, the node on which the allocated physical memory is located may be derived from the allocation request thereby facilitating application level, allocation of specified portions of physical memory.

Abstract: A design verification system comprising a set of modular verification engines invoked by a framework that manages the control flow between the engines. The framework receives a verification problem from an application and attempts to solve it by instantiating one or more engine in a customizable sequence or set of sequences. Each verification engine is configured to achieve a specific verification objective and may be coded against a common API to facilitate exchange of information between the engines. The verification engines may include reduction engines, which attempt to simplify a problem by modifying it or decomposing it, and decision engines, which attempt to solve problems that are passed to them. As a verification problem is passed from one engine to the next, the engine may alter the verification problem such that a decision engine at the end of the sequence may receive a verification problem that is simpler to solve than the original problem specified by the system user.

Abstract: A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and while the barrier operation is pending, a load request associated with the load instruction is speculatively issued. A speculation flag is set to indicate the load instruction was speculatively issued. The flag is reset when an acknowledgment of the barrier operation is received. Data that is returned before the acknowledgment is received is temporarily held, and the data is forwarded to the register and/or execution unit of the processor only after the acknowledgment is received. If a snoop invalidate is detected for the speculatively issued load request before the barrier operation completes, the data is discarded and the load request is re-issued.

Abstract: A system for transmitting and receiving data between the near end to the far end of a transmission line. The system has simultaneous bi-directional (SBIDI) drivers and receivers for high performance over well behaved transmission lines. The SBIDI drivers and SBIDI receivers are enabled and disabled by logic inputs. A unidirectional (UNI) receiver is connected in parallel with each SBIDI receivers. Logic insures that the SBIDI and UNI receivers are not enabled at the same time. When desired, the SBIDI receivers are disabled and the UNI receivers enabled and signaling is done unidirectional. The current level in the SBIDI drivers may be modified in response to mode compensation signals to improve signal to noise in the unidirectional mode and to compensate for losses in the simultaneous bi-directional mode. The system may be integrated into all I/O's for maximum design flexibility.