Abstract: An integrated circuit having improved planarity includes a substrate, a plurality of transistors integrated into a top surface of the substrate, and a plurality of insulating layers over the top surface which are interleaved with respective sets of signal conductors. These signal conductors are spaced apart on the insulating layers and are routed through holes in the insulating layers to the transistors in order to carry signals to and from the transistors. Also, in accordance with the invention, the integrated circuit further includes dummy conductors on the insulating layers in the spaces between the signal conductors. These dummy conductors are open circuited and consequently carry no signals. Their function is purely mechanical; and specifically, they function to partially fill the spaces between the signal conductors such that an overlying insulating layer can be formed without peaks and valleys.

Abstract: A speed-up circuit is employed in a semiconductor chip of the type that includes a P-type substrate with a plurality of NPN transistors integrated into a surface thereof. Those transistors include a first NPN transistor having a base which receives a control signal, a collector coupled to a voltage bus, and an emitter which drives a first resistor plus a base of a second NPN transistor plus a small parasitic capacitance. The second NPN transistor has a collector coupled to a voltage bus, and an emitter which drives a second resistor plus a larger parasitic capacitance. And, the speed-up circuit is comprised of: a PNP transistor having an emitter coupled to the large capacitance, a base coupled to a tap on the first resistor, and a collector coupled to the substrate.

Abstract: Data bits are decoded from a composite signal that is formed by coding multiple bit sequences with respective spreading codes, and transmitting the coded bit sequences simultaneously and asynchronously over a single channel in which the bit sequences are added. This decoding involves a metric in combination with a repetitive decision process which is only linearly dependent on the number of bit sequences in the composite signal.

Abstract: A machine for bonding leads from a chip to a substrate having top and bottom surfaces that are non-coplanar is comprised of a carrier for the substrate which includes a frame having a set of stops that terminate in a single plane and which are arranged in a pattern with a central opening. Also included in the carrier is a forcing mechanism which pushes on the bottom surface of the substrate such that the top surface of the substrate is pinned directly against all of the stops simultaneously and a portion of that top surface is exposed through the opening. This causes the exposed portion of the substrate's top surface to be aligned with the plane of the stops regardless of the degree of non-coplanarity that exists between the substrate's top and bottom surfaces.

Abstract: A leak in an enclosure of an integrated circuit package is detected by the steps of: filling the enclosure with a first gas at the time the enclosure is sealed; subsequently enveloping the integrated circuit package with a second gas that is different than the first gas; holding the second gas at a constant pressure over a certain time period; and sensing a surface of the enclosure, during the above steps, for the presence of microscopic deflections. If the enclosure has a gross leak, no deflection will occur when the package is initially enveloped with the second gas. If the package has a minor leak, a deflection will occur when the package is initially enveloped with the second gas, and the amount of the deflection will decrease during the holding time period.

Abstract: A liquid cooled integrated circuit module includes a substrate, a plurality of chips mounted on the substrate, and electrical conductors integrated into the substrate to interconnect the chips. A compliant member which is completely seamless overlies all of the chips. This seamless compliant member is hermetically sealed at its perimeter to the substrate around all of the chips. Between this seamless compliant member and the chips are thermally conductive studs, and they carry heat by conduction from the chips to the compliant member. A rigid cover overlies the compliant member, and it is attached to the substrate at its perimeter. Within the cover are several parallel spaced apart ribs which project towards and press against the compliant member between the chips, and they form channels for a liquid coolant which carries heat away from the compliant member.

Abstract: Enhanced density of electrical and/or mechanical interconnections between adjacent wafers within integrated circuit assemblies and structural integrity of those interconnections under temperature cycling conditions, is attained by utilizing laser assisted chemical vapor deposition to fabricate precisely configured metal posts which serve as such interconnections.

Abstract: A multiplier circuit is comprised of multiple arrays of logic cells. Each array has input lines for receiving two multibit binary numbers that are to be multiplied together; and each logic cell includes an AND gate for producing single power product terms by multiplying together one bit from each of the two numbers. These cells are arranged in the arrays such that the total quantity of single power product terms of any particular power in the respective arrays is within 30% of each other. One subset of cells of each array also includes a respective two-bit adder, and another subset of cells of each array includes a respective three-bit adder. These two-bit and three-bit adders are interconnected within each array to form an intermediate result, in parallel with the other arrays, which consists of a partial sum of all product terms in the array together with no more than one remaining carry-in for each bit of that partial sum.

Abstract: A synchronizer is comprised of a voltage amplifier having an input terminal for receiving a voltage sample and an output terminal for generating an output voltage that is inversely proportional to the voltage of the input terminal. Also, a first feedback circuit couples the output terminal to a control transistor internal to the amplifier, and a second feedback circuit couples the output terminal to the input terminal. The first feedback circuit together with the control transistor has a fast response time, in comparison to the second feedback circuit; and it operates to quickly increase the output voltage when the voltage sample on the input terminal is below a predetermined level, and vice versa, without altering the voltage sample on the input terminal. And, the second feedback circuit operates to slowly modify the voltage sample on the input terminal in inverse proportion to the output terminal voltage.

Abstract: An electrostatic discharge protection circuit includes a P.sup.- doped channel and an N.sup.- doped channel that form a serial path between a signal pad and a transistor. Holes are depleted from the P.sup.- doped channel in response to a negative electrostatic discharge on the input signal pad; and electrons are depleted from the N.sup.- doped channel in response to a positive electrostatic discharge on the input signal pad. When either depletion occurs, the path from the signal pad to its transistor is open circuited; and so the transistor is protected. Conversely, when no electrostatic charge exists on the signal pad, the path through the P.sup.- doped channel and the N.sup.- doped channel is highly conductive; and so signals pass between the pad and the transistor very quickly.

Abstract: A method of fabricating a tapered via hole in a polyimide layer of an integrated circuit includes the steps of: disposing a layer of SiO.sub.2 on the polyimide layer and a layer of photoresist on the SiO.sub.2 such that the layers have an opening which exposes a region of the polyimide layer for the via hole; etching the exposed polyimide region partway through the polyimide layer, while simultaneously etching back the photoresist on the sidewalls of the opening to thereby uncover a strip of SiO.sub.2 adjacent to the perimeter of the exposed polyimide region; enlarging the exposed region of the polyimide by etching the uncovered strip of SiO.sub.2 ; and repeating the etching step and enlarging step a predetermined number of times.

Abstract: This invention is an improvement to an integrated circuit package which is of a type that includes a package body with multiple chip attach regions for holding respective integrated circuit chips, signal pads around the chip attach regions, an array of I/O pins on the package body, a first set of conductors in the package body which selectively connect some of the signal pads to the I/O pins, and a second set of conductors which selectively connect some of the signal pads to each other but not to any I/O pins.

Abstract: An easily installable and easily expandable electromechanical memory assembly for a data processing system includes: a frame having a backplane, a plurality of printed circuit board connectors on the backplane, and conductors on the backplane which interconnect the connectors; a controller on a printed circuit board which is plugged into one of the connectors and consists essentially of logic circuitry for generating and receiving control signals on the backplane conductors; and multiple data storage units; each unit being mounted on a separate printed circuit board, plugged into a separate connector, and consisting essentially of a mechanical drive mechanism which reads data by physically moving a data storage medium past a data sensor in direct response to the control signals from the controller on the backplane conductors.

Abstract: In a communication network, a transmitting station sends encrypted messages for selective decryption in any one of several receiving stations. To that end, the transmitting station stores a single set of several encryption keys, each of which is for encrypting messages to all of the receiving stations. Also, for each message that is sent for decryption in a particular receiving station, the transmitting station (a) automatically selects at random any encryption key from the single set, (b) receives, from an input terminal, a control word which is a series of bits that uniquely identifies the particular receiving station, (c) encrypts both the message and the control word with the randomly selected key, and (d) transmits the result of step (c) to all of the receiving stations.

Abstract: A liquid cooled electronic circuit includes a printed circuit board having two oppositely facing surfaces, electronic components mounted on one of the two surfaces, and conduits which carry a liquid and touch the electronic components to cool them; wherein a frame is also provided for holding the conduits snugly against the components without overstressing the printed circuit board. This frame is characterized as having: (a) a first set of contacts which engage the conduits; (b) a second set of contacts which engage the surface of the printed circuit board opposite the one surface; (c) the contacts of the second set being spaced apart and located at predetermined distances from the board's perimeter; and (d) fasteners for urging the conduits against the electronic components by moving the first and second sets of contacts toward each other with the conduits, the electronic components, and the printed circuit board lying therebetween.

Abstract: A multichip integrated circuit package comprises a thin planar body which has top and bottom major surfaces. Conductors, for carrying electrical signals, are integrated into the body and include input/output terminals on one portion of the bottom surface. Downward-facing cavities for holding respective high power integrated circuit chips extend from another portion of the bottom surface into the body, and upward-facing cavities for holding respective low power integrated circuits extend from the top surface into the body. Small thermal resistance for the high power chips is achieved, and footprint is simultaneously minimized by locating the upward-facing cavities over the terminals.

Abstract: An assembly for cooling an array of IC packages which have respective non-coplanar heat dissipating surfaces, comprises: a frame that is attachable to the array and has multiple beams, each of which is positioned to overlie some of the IC packages; respective liquid-cooling jackets for the IC packages with each jacket having a heat absorbing face; each jacket being mounted via a post that is loosely fitted through a respective hole in one of the beams in proximity with a respective one of the IC packages; and each jacket mounting providing a flexible connection which allows the jacket's heat absorbing face to be placed at multiple angles and different heights, and thereby coincide with the non-coplanar heat dissipating surface of an IC package.

Abstract: A data processing system includes a plurality of data processing modules coupled to a bus and to a set of control lines. These modules request the use of the bus by sending respective sequences of at least two binary numbers during successive cycles on the control lines in synchronization with each other. On the control lines the numbers are logically ORed together. Each module terminates the sending of its numbers if, during any one of the successive cycles, the logical OR is greater than twice the number which the module itself is sending. A module uses the bus only if, during each of the successive cycles, the logical OR does not exceed the number which the module itself sends.

Abstract: A method of soldering component leads to I/O pads on a printed circuit board, without desoldering any other circuit components which were previously soldered to the board near the pads, includes the steps of: forming a mechanical assembly in which respective joints of the pads and the leads and respective solder mounds are mechanically held together; moving the assembly at a predetermined speed on a conveyor such that the joints, but not the previously soldered components, sequentially pass through a target area which is small relative to the total number of joints; and melting and then hardening the solder mounds, without desoldering the previously soldered components, by directing a focused stream of hot gas at the target area as the joints move therethrough on the conveyor.

Abstract: A fixture is provided which cleans a plasma etcher of a type that has a holding member with a surface which holds wafers that are to be etched, and an enclosing member which encloses the holding member to form a chamber for the plasma. This fixture operates to produce a large voltage change near the enclosing member and thereby enable the cleaning of the enclosing member by the plasma itself. To achieve such a large voltage change, the fixture is configured to fit inside of the enclosing member, provide a surface which is substantially larger than the surface of the holding member, and make electrical contact with the surface of the holding member. Preferably, the surface provided by the fixture is at least 50% larger than the surface of the holding member.