Abstract: A single integrated antenna feed transmits and receives electromagnetic waves in the C, X, and Ku frequency bands. This antenna feed includes an inner metal tube which lies along a central axis, and an outer metal tube which surrounds and is coaxial with the inner metal tube. Through the inner tube, a passageway is provided which is sized to carry electromagnetic waves in the X-band and Ku-band, but reject electromagnetic waves in the C-band. Between the inner tube and the outer tube, another passageway is provided which is sized to carry electromagnetic waves in the C-band. An I/O port for the X and Ku-bands is provided by a first end of the inner tube, and an I/O port for the C-band is provided by a corresponding first end of the outer tube. This first end of the outer tube lies proximate to but not past the first end of the inner tube. A solid dielectric is inserted into and fills the first end of the inner tube; and, a hollow metal cone is attached to the first end of the outer tube.

Abstract: An electronic transmitter transmits multiple digital input signals simultaneously by including an encoding circuit, a digital combiner circuit, and a modulator circuit. The encoding circuit encodes each of the digital input signals as a sequence of "1" and "0" chips with all of the chip sequences being synchronized in parallel; the digital combiner circuit generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in the synchronized chip sequences; and, the modulator circuit generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of the signed multi-bit digital signal.

Abstract: A CDMA communication system is provided in which bit rates are dynamically allocated by a single CDMA receiving station to a plurality of CDMA transmitting stations, all of which are intercoupled to each other over a CDMA channel and a feedback channel. Each CDMA transmitting station includes a control circuit which sends control signals on the CDMA channel in spaced apart time intervals which request respective bit rates on the CDMA channel; and, the CDMA receiving station includes a bit rate allocating circuit which receives and responds to the control signals by sending feedback messages over the feedback channel that address individual CDMA transmitting stations and grant respective bit rates to the addressed station. In one preferred embodiment, each transmitting station includes a data buffer which stores a time varying number of data bytes that are to be sent, and each transmitting station requests respective bit rates on the CDMA channel by including that number in the control signals.

Abstract: In one method according to the present invention, an integrated circuit chip is fabricated by the following steps:1) providing a trial layout in the chip for a victim net and a set of aggressor nets which have segments that lie next to the victim net;2) assigning to the trial layout of the victim net, the parameters of--a line capacitance, a line resistance, and a driver output resistance; and assigning to the trial layout of each aggressor net, the parameters of--a coupling capacitance to the victim net, and a voltage transition;3) estimating, for each aggressor net, a respective peak crosstalk voltage V.sub.p which the aggressor net couples into the victim net as a function V.sub.p =K(e.sup.-X -e.sup.

Abstract: A memory in an integrated circuit chip includes an array of memory cells and a read/write circuit which performs precharge and sense operations on the array for a time interval that is set by the width of a pulse signal. This pulse signal is generated by a pulse generator circuit which contains transistors that switch on and off at an unpredictable speed; and consequently, the width of the pulse signal has a large tolerance. To decrease this large tolerance in the pulse signal, a compensation circuit is provided which includes a plurality of compensation components for the pulse generator. This compensation circuit selectively couples the compensation components to the pulse generator such that the selectively coupled components in combination with the pulse generator's transistors produce the pulse signal with a precise width that has an insignificant tolerance.

Abstract: A dual frequency waveguide switch passes electromagnetic waves in the X-band along one route, and passes electromagnetic waves in the Ku-band along a different route. This switch includes a housing which has first, second, and third openings for the electromagnetic waves to pass through; and a movable member, mounted in the housing, having first and second passageways. The first passageway is shaped to pass electromagnetic waves in both the X-band and the Ku-band, and the second passageway is shaped to pass electromagnetic waves in the Ku-band but reject electromagnetic waves in the X-band. A forcing mechanism forces the moveable member to a position "A" in the housing where the first passageway interconnects the first opening to the second opening, and to a position "B" where the second passageway interconnects the first opening to the third opening.

Abstract: A multipoint-to-point CDMA communication system comprises a plurality of CDMA transmitting stations and a single CDMA receiving station, all of which are intercoupled to each other over one CDMA channel and one feedback channel. On the one CDMA channel, the plurality of CDMA transmitting stations simultaneously send respective CDMA signals to the receiving station. In the receiving station, respective time differences are measured between a reference clock signal and the spreading codes in the CDMA signals from each of the CDMA transmitting stations; and these time differences are indicated in respective error signals which the CDMA receiving station sends on the feedback channel to each of the CDMA transmitting stations. Each CDMA station responds to its error signals by time shifting its spreading code such that it arrives in the receiving station in synchronization with the reference clock signal.

Abstract: An electromechanical module comprises an IC package having a top surface which dissipates heat and a heat sink which is held by a frame in direct thermal contact with the top surface. This frame includes a pair of spaced-apart elongated beams and a pair of end members which connect to opposite ends of the beams; and the beams together with the end members surround the IC package and expose all of the top surface. Thus, the heat sink can be in direct thermal contact with all of the top surface and can extend past it without having to step up to get over the frame. To attach/remove the frame from the IC package, each end member has at least one leg with a lip that catches on the bottom surface of the IC package; and, when the beams are manually bowed, the lips on the legs move further apart and past the bottom surface.

Abstract: A heat transfer module, comprises: a heat generating unit and a heat receiving unit which are separated by a gap; a compliant body, having microscopic voids therethrough, which is compressed into the gap; and a liquid metal alloy that is absorbed in the microscopic voids in the compliant body. Further, the heat transfer module also includes a seal ring in the gap which surrounds the compliant body and which is spaced apart from the compliant body; and, the compliant body is intentionally compressed so much that a portion of the liquid metal alloy is squeezed from the compliant body into the space between the compliant body and the seal ring. Squeezing liquid metal alloy from the compliant body lowers the thermal resistance between the heat generating unit and the heat receiving unit by increasing the area through which heat is transferred and by increasing the thermal conductivity through the compliant body.

Abstract: A sub-assembly for transferring heat between a heat generating unit and heat receiving unit which are separated by a gap, comprises: a compliant body having microscopic voids therethrough; a liquid metal alloy that is absorbed in the microscopic voids in the compliant body; a seal ring which surrounds the compliant body; and, a retaining member which is attached to the compliant body and the seal ring, and which holds the compliant body spaced apart from the seal ring. This sub-assembly is placed in the gap between the two units and compressed to the point where liquid metal alloy is squeezed out of the compliant body. Squeezing liquid metal alloy from the compliant body lowers the thermal resistance between the heat generating unit and the heat receiving unit by increasing the area through which heat is transferred and by increasing the thermal conductivity through the compliant body.

Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the present invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of an equation.

Abstract: A bridge circuit includes a microprocessor having a first I/O port which couples to a SCSI bus and a second I/O port which is coupled through transceivers to an EISA bus. Also, the bridge circuit includes an EISA interface controller, having control lines coupled to the EISA bus and the transceivers, which enable the microprocessor to request and use the EISA bus in time-shared fashion. In order to achieve a high speed of operation, the bridge circuit further includes a memory module, coupled via a private bus to the second I/O port of the microprocessor, which sends instructions on the private bus directly to the microprocessor, without generating any signals on the EISA bus. In addition, in order to prevent deadlocks on the private bus, the bridge circuit includes a deadlock prevention circuit which is coupled to the microprocessor and the private bus and the EISA interface controller.

Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the preset invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of a table.

Abstract: An electronic tester, for testing I.sub.ddq in an integrated circuit chip, comprises: 1) a first power supply, having a large current capacity, which sends current to the chip through a first diode; 2) a second power supply, having a current sensor and a small current capacity which is substantially less than the large current capacity, which sends current to the chip through a second diode which is in parallel with the first diode; and 3) a control module which sends test vectors to the chip during a series of spaced apart T.sub.A time intervals, and sends control signals to at least one of the power supplies which indicate when the T.sub.A time intervals occur. In response to the control signals, the one power supply generates a first output voltage during the T.sub.A time intervals which forward biases said first diode and reverse biases said second diode; and it also generates a second output voltage between the T.sub.

Abstract: Messages are routed through an array of data processing nodes which are intercoupled with channels in rows and columns. Under certain conditions, a message can exit a node in either one of two directions; and this enables the message to reach its destination by multiple routes. Under other conditions, the message must exit the node in only predetermined direction, and that direction is selected to avoid message routing deadlocks.

Abstract: A multipoint-to-point CDMA communication system comprises a plurality of CDMA transmitting stations and a single CDMA receiving station, all of which are intercoupled to each other over one CDMA channel and one feedback channel. On the one CDMA channel, the plurality of CDMA transmitting stations simultaneously send respective CDMA signals to the receiving station. In the receiving station, respective time differences are measured between a reference clock signal and the spreading codes in the CDMA signals from each of the CDMA transmitting stations; and these time differences are indicated in respective error signals which the CDMA receiving station sends on the feedback channel to each of the CDMA transmitting stations. Each CDMA station responds to its error signals by time shifting its spreading code such that it arrives in the receiving station in synchronization with the reference clock signal.

Abstract: A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consist essentially of silicon, having a crystalline grain size which is smaller than polycrystalline with dopant atoms that are interstitial in the silicon. Process temperatures are limited such that the dopant atoms remain interstitial and do not become substitutional.

Abstract: In a multiprocessor system, at least one processor is acting as a master processor and another processor is acting as the slave or shadow processor that checks operation of the first processor. Periodically, a controller switches operating mode of a master or main processor to slave or shadow mode, and at the same time switches operation of a slave or shadow processor to main or master processing mode. The first processor is then used as a slave or shadow processor to check operation of the second processor.

Abstract: A multiprocessor data processing system comprises a plurality of unsymmetrically connected data processing nodes; where the total number of nodes is more than 2.sup.n-1 and less than 2.sup.n, and n is an integer larger than two Each node has n input/output channels which respectively are channel(0), channel(1), channel(2), etc.; each node has a binary address b.sub.n-1. . . b.sub.1 b.sub.0 which runs consecutively from node to node; each pair of nodes whose binary addresses differ by only one binary bit b.sub.x are interconnected by a channel(x) to channel(x) connection; and, at least one pair of nodes whose binary addresses differ by two binary bits b.sub.x and b.sub.y are interconnected by a channel(x) to channel(y) connection, where x and y=0,1, . . . n-1. To establish a route from any one node to any other node, channels are selected which decrease the distance to the destination by two nodes or one node or maintain the same distance.