Abstract: An integrated circuit tester includes a fail-safe mechanism for moving an integrated circuit chip between an initial position where the integrated circuit chip is inserted into the tester, and a test position where the integrated circuit chips is actually tested. This fail-safe mechanism includes a motor and a shaft which the motor rotates to move the integrated circuit chip. An electronic control circuit can be included to automatically stop the motor when the integrated circuit reaches its initial position, or its test position; but if the control circuit fails to operate properly, then damage to the integrated circuit tester is prevented by the fail-safe mechanism.

Abstract: An initial stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple sets of input registers which store respective addresses; and an address modifying circuit that is coupled to the input registers, which receives commands, and in response, selects one register in one set and generates a modified address by performing arithmetic operations on the address in the selected register. Also, the initial stage includes a boundary check circuit that is coupled to the address modifying circuit, which stores a respective minimum limit and a respective maximum limit for each register set. This initial stage is particularly useful in generating sequences of addresses for memory cells in a chip that is to be tested, where the cells are arranged in rows and columns. When a particular Min/Max limit for a row/column is reached, then that event is remembered by the boundary check circuit.

Abstract: A stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the steps of: 1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device; 2) receiving a signal in the controller from the I/O device at any time during the sending step, to terminate the transmission burst; 3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent; 4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and, 5) repeating the above steps until the stream of data is received in its entirety by the I/O device.

Abstract: Multiple streams of digital video data are partitioned into frames of at least two different lengths, where each frame length is an integer multiple times a minimum frame length. Each frame is written into a series of full cells and one or two partial cells. Each full cell carries the same number of video data bits, while each partial cell carries video data bits and/or other overhead bits which together equal the number of video data bits in one full cell. All of the full cells and partial cells for the frames are sent in a time-multiplexed fashion on a communication channel at a single cell rate. A constraint is imposed whereby the different frame lengths are limited to those where the integer multiple of the minimum frame length, divided by the total number of full and partial cells per frame, is a single ratio; and consequently, the video data bits in all of the video streams occur on the communication channel at the same average bit rate, independent of the different frame lengths.

Abstract: An electromechanical apparatus for testing IC chips includes a chip holding subassembly, a power converter subassembly, and a temperature regulating subassembly which are squeezed together in multiple sets by respective pressing mechanisms; and this apparatus uses a generic structure for both the chip holding subassembly and the power converter subassembly. This generic structure is comprised of a planer substrate having first and second faces that are opposite to each other and are surrounded by an edge that is free of any electrical edge connectors. To use the above generic subassembly as the chip holding subassembly, an electrical components on the first face of the substrate include sockets which hold the chips that are tested. To use the above generic subassembly as the power converter subassembly, the electrical components on the first face of the substrate include electrical power converters for the chips that are tested.

Abstract: An alloy film is fabricated, on the face of a heat exchanger for an integrated circuit, by a process that dispenses various liquids onto the heat exchanger's face. To prevent those liquids from falling off of the heat exchanger's face onto other components which hold the heat exchanger on a frame, the process begins by combining the heat exchanger into an assembly that includes a retainer and a compliant member. The retainer catches any liquids that fall off the heat exchanger's face, and the compliant member forms a seal between the heat exchanger and the retainer which prevents the liquids from leaking onto the other components.

Abstract: A power system includes an output voltage terminal that is coupled by a first conductor to one pressed power contact which is then coupled by a second conductor to an electronic device. Also, the electronic device is coupled by a third conductor to one pressed signal contact which is then coupled by a fourth conductor to an output voltage feedback terminal on the power supply. Further, the power system includes a fault detection circuit which is coupled to the fourth conductor. In operation, the fault detection circuit senses if the pressed signal contact is open at a time when the pressed signal contact is supposed to be closed. If an open contact is sensed, the fault detection circuit sends a signal to an operator which indicates that corrective action is needed.

Abstract: An output stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple input registers which hold input addresses and input data words; and a multiplexer circuit, having a plurality of parallel data inputs which concurrently receive the input addresses and the input data words, having control inputs for receiving a sequence of control signals, and which generates serial bit streams by selectively passing bits from the input addresses and input data words in response to the control signals. These serial bit streams from the multiplexer circuit preferably include a first bit stream which defines a data input to an integrated circuit chip that is to be tested, and a second bit stream which defines an expected output from the chip corresponding to the first bit stream.

Abstract: A mechanical assembly is comprised of a heat exchanger for an integrated circuit. In the assembly, a retainer for a liquid has a bottom with an opening thru which the heat exchanger extends such that a face of the heat exchanger is surrounded by the retainer. Also in the assembly, a compliant member forms a seal for the liquid between the heat exchanger and the retainer. This mechanical assembly is useful in fabricating an alloy film on the heat exchanger's face.

Abstract: An intermediate stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of a plurality of input address registers which hold respective input addresses; and a memory address generator, coupled to the input address registers, which generates a series of memory addresses by selecting bits from the input addresses. A memory is coupled to the memory address generator, which sequentially receives each memory address in the series; and in response, this memory sends a corresponding series of translated addresses to a memory output. Multiple output registers are coupled to the memory output, and each output register stores a respective translated address in the series. With this intermediate stage, the input addresses can be virtual addresses in a virtual, or hypothetical, memory; and, those virtual addresses can be translated into physical addresses for an actual memory chip that is to be tested.

Abstract: A method of selectively establishing any one connection of several different types, between a client program in a first computer and a server program in a second computer, includes the following steps. Initially, a control program is provided in the first computer which receives a command with parameters, from the client program, that specify the one type of connection which is to be established. In response, the control program automatically constructs a particular pipename which includes the parameters in a format that differs for each different type of connection. Thereafter, the control program tranmits the pipename which it constructed to a communications program in the second computer. Subsequently, the control program receives a result from the communications program which indicates whether or not the communications program used the pipename to successfully establish the one type of connection to the server program. Then, the control program notifies the client program of the result.

Abstract: A multi-stage algorithmic pattern generator, which generates bit streams for testing IC chips, is comprised of an initial stage, an intermediate stage, and an output stage which are coupled together as a three stage pipeline. The initial stage sequentially generates multiple sets of virtual addresses for a virtual memory in response to a series of instructions from an external source. The intermediate stage sequentially stores each set of virtual addresses from the initial stage and translates the stored set of virtual addresses into a set of physical addresses for an actual memory that is to be tested. The output stage sequentially stores each set of physical addresses from the intermediate stage and generates output signals for testing the memory chips, by selecting bits from the stored set of physical addresses.

Abstract: A system for testing IC chips selectively with stored or internally generated bit streams is comprised of a memory which stores instructions of a first class that expressly recite a first bit stream, and stores instructions of a second class that specify operations which generate a second bit stream. A first pattern generator is coupled to the memory, which sequentially reads the instructions of the first and second classes. The first pattern generator includes a time-shared control circuit which sends the first bit stream to a test port on the chips that are tested in response to the first class instructions that are read. In addition, a second pattern generator is coupled to the first pattern generator. This second pattern generator receives the second class instructions that are read; and in response, it sequentially generates portions of the second bit stream by performing the operations which the second class instructions specify.

Abstract: A temperature control system comprises a reservoir that is holding a hot fluid; a heat exchanger, for an electronic component, coupled to an input conduit that carries the hot fluid from the reservoir into the heat exchanger; an output conduit coupled to the heat exchanger, that carries the hot fluid from the heat exchanger back to the reservoir; a first temperature sensor, coupled to the input conduit; and a second temperature sensor, coupled to the output conduit. A heater is coupled to the output conduit which adds heat to the hot fluid in the output conduit in response to a heater control signal; and a cooler is coupled to the reservoir which adds cold fluid to the reservoir in response to a cooler control signal. A temperature controller generates the heater control signal and the cooler control signal as respective functions of both sensed temperatures.

Abstract: A system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. If the code indicates that the number of bit streams in a set is only one, then that one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more than one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary.

Abstract: A video system is comprised of: a) a single supervisor processor, and multiple co-processors which are selectable in number and are coupled via a bus to the single supervisor processor; b) a supervisor memory which is coupled to the supervisor processor and which stores a respective portion of each of several video streams; c) a control program in each co-processor which selectively reads the stored video stream portions from the supervisor memory and sends each video stream portion that is read to a different viewer; and d) a control program for the single supervisor processor, which dynamically updates the stored portion of each video stream in the supervisor memory and which services external requests to change the respective viewers of each video stream. In this video system, the number of co-processors is selectable; the number of video streams which are sent by each co-processor is selectable; and, the number of viewers per stream is selectable.

Abstract: A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested; and so in response to the programmable commands, the clock signal is sent sequentially to the chips that are to be tested, in selectable subsets.

Abstract: A system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams that are readable one word at a time. In operation, each pattern generator selectively reads the bit streams, word by word, from its respective memory; and its sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. While that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel. Since all of the pattern generators operate in parallel, and since each pattern generator sends bit streams to all of the chip driver circuits that are coupled to its bus simultaneously, a high speed of operation is attained.

Abstract: An I/O device is shared between a host operating system, and a foreign operating system that runs under the host operating system, in a single computer. The I/O device must be of a type which includes a port driver that receives device commands for reading addressable fields on a removable data storage media. Each media which is to be a source of data for the host operating system stores a first identifier in a particular addressable field, and each media which is to be a source of data for the foreign operating system stores a second identifier in a particular addressable field. A registry in the host operating system indicates that the I/O device is to be used exclusively by the host operating system; so the host will try to use the I/O device. But in addition, a different private registry in the foreign operating system indicates how that operating system can address the I/O device; so the foreign operating systems will also try to use the I/O device.

Abstract: A connector for sending power to an IC-chip thru two pressed joints in series; includes a solid block having a top surface, a bottom surface, and a side with a slot that extends from the top surface to the bottom surface; and 2) a springy strip of metal having a center section which is held by the slot in the block. The springy strip also has a first end section which extends from the center section and includes a springy input contact that is cantilevered above the top surface of the block. The springy strip further has a second end section which extends from the center section and includes a springy output contact that is cantilevered below the bottom surface of the block.