Patents Represented by Attorney, Agent or Law Firm Charles J. Fassbender
  • Patent number: 5818886
    Abstract: A pulse synchronizing module includes: a) a pair of input leads which respectively receive a clock signal and digital input pulses that are asynchronous to the clock signal; b) a first counter circuit which is triggered by rising edge transitions in the input pulses, and a second counter circuit which is triggered by falling edge transitions in the input pulses; c) first and second registers which, in synchronization with the clock signal, sample respective counts in the first and second counter circuits; and d) an output circuit, coupled to the first and second registers. This output circuit generates, the rising edge of an output pulse, in synchronization with the clock signal, when the count sample in the first register differs from the number of rising edges which the output circuit previously generated; and it generates the falling edge of the output pulse, in synchronization with the clock signal, when the count sample in the second register differs from the number of falling edges previously generated.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: October 6, 1998
    Assignee: Unisys Corporation
    Inventor: David Edgar Castle
  • Patent number: 5813034
    Abstract: A multi-level distributed data processing system includes: 1) a system bus having a main memory coupled thereto; 2) multiple high level cache memories, each of which has a first port coupled to the system bus and a second port coupled to a respective processor bus; and, 3) each processor bus is coupled to multiple digital computers through respective low level cache memories. Further, each low level cache memory stores data words with respective tag bits which identify each data word as being shared, modified or invalid but never exclusive; and, each high level cache memory stores data words with respective tag bits which identify each data word as being shared, modified, invalid, or exclusive.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: September 22, 1998
    Assignee: Unisys Corporation
    Inventors: David Edgar Castle, Greggory Douglas Donley, Laurence Paul Flora
  • Patent number: 5794011
    Abstract: A performance regulator program monitors and controls in real time, the performance level which an application program achieves when it is executed on a digital computer. With this performance regulator program, any external units which are coupled to the computer are prevented from being overloaded by excessive performance in the application program. Also with this performance regulator program, several models of the application program can be easily generated such that each model achieves a different performance level.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: August 11, 1998
    Assignee: Unisys Corporation
    Inventors: Derek William Paul, Loren C. Wilton, Frederick Joseph Barker
  • Patent number: 5793797
    Abstract: An electronic data transmission system has a low peak-to-average power ratio by including a transmitter circuit which receives an input signal and in response generates a distorted output signal. This distorted output signal is generated by amplifying the input signal with one particular gain when the input signal is at a maximum magnitude which gives the distorted output signal a corresponding maximum magnitude, and by amplifying the input signal with a larger gain when the input signal is in a predetermined range below the maximum magnitude. The distorted output signal travels over a communication channel to a receiver circuit, which regenerates the input signal by amplifying the distorted output signal with a gain that is the inverse of the gain by which the distorted signal is generated.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: August 11, 1998
    Assignee: Unisys Corporation
    Inventors: Thomas Robert Giallorenzi, David William Matolak, Johnny Michael Harris, Robert William Steagall, Bruce Howard Williams
  • Patent number: 5737754
    Abstract: A cache memory includes: a plurality of tag memory blocks, each of which stores multiple compare addresses; a first bus which sends a low order address to all of the tag memory blocks; a respective output from each tag memory block on which a compare address is read in response to the low order address; a second bus which carries a high order address; and, a comparator circuit which generates a miss signal when the compare address on the output from every tag memory block miscompares with the high order address. Each tag memory block further stores respective control bits with each compare address; and each tag memory block responds to the low order address by reading the compare address and the respective control bits, in parallel, on its respective output.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: April 7, 1998
    Assignee: Unisys Corporation
    Inventor: David Edgar Castle
  • Patent number: 5731725
    Abstract: A precision delay circuit in an integrated circuit chip includes a transistor switching circuit in combination with a control circuit and a compensation circuit. The transistor switching circuit receives an input signal; and in response, the transistors switch on and off at an unpredictable speed to generate an output signal with a delay that has a large tolerance. The control circuit estimates the unpredictable speed at which the transistors switch and it generates control signals that identify the estimated speed. The compensation circuit includes a plurality of compensation components for the transistor switching circuit. This compensation circuit receives the control signals from the control circuit; and in response, it selectively couples the compensation components to the transistor switching circuit such that the combination of the transistors and the selectively coupled components generates the output signal with a precise delay that has an insignificant tolerance.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: March 24, 1998
    Assignee: Unisys Corporation
    Inventors: Roland D. Rothenberger, Greg T. Sullivan, Kenny Yifeng Tung
  • Patent number: 5724229
    Abstract: A pressure-mountable, electro-mechanical assembly includes a housing which holds an integrated circuit chip in an open cavity; and, the housing has conductors that connect the chip to a pattern of metal pads on an exterior surface of the housing. A lid lies on the exterior surface of the housing, covers the cavity, and has terminal holes that match and expose the pattern of metal pads. Respective conductive springs are held in the terminal holes, contact the metal pads, and project from the lid. This lid operates as both a protective cover for the chip and a carrier for the springs.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: March 3, 1998
    Assignee: Unisys Corporation
    Inventors: Jerry Ihor Tustaniwskyi, Leonard Harry Alton, Ronald Jack Kuntz, Ronald Allen Norell
  • Patent number: 5710938
    Abstract: A data processing array is partitioned by electronic control signals into multiple sub-arrays which are established and operate independently of each other. In the preferred embodiment, an operator's console is provided for manually selecting the data processing nodes that are in each sub-array, and a control module is coupled by control channels between the console and the data processing nodes. These control channels carry the control signals directly to the data processing nodes without utilizing the input/output channels which are intercoupled to form the array. One portion of these control signals prevent each node in a sub-array from sending messages on the input/output channels to any node in another sub-array; and another portion of the control signals select a node in each sub-array as a boot node from which a separate operating system and user programs are loaded without utilizing the input/output channels.
    Type: Grant
    Filed: July 19, 1995
    Date of Patent: January 20, 1998
    Assignee: Unisys Corporation
    Inventors: Curtis Wayne Dahl, Daniel Allen Neuss, Mark Steven Collett, Mark Elliot Bsharah
  • Patent number: 5699522
    Abstract: A data processing system includes a digital computer that has a plurality of data processing programs. A set of upgraded stations is coupled to the computer which generate messages that employ a relatively simple format to select the data processing programs; and a set of older stations is also coupled to the computer which generate messages that employ a complex format to select the data processing programs. A message routing program in the computer receives all of the messages from the stations, analyzes each message that has the simple format to identify the selected data processing program, and sends the message directly to the selected program. By comparison, the message routing program sends each message that has the complex format to a secondary routing program; and this secondary routing program analyzes each message which it receives, identifies the selected data processing program, and sends the message to the selected program.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: December 16, 1997
    Assignee: Unisys Corporation
    Inventors: Clifford Shiroku Shimizu, Patricia Lynn Walsh, Anthony La Vel Crider
  • Patent number: 5694432
    Abstract: An electronic transmitter for a digital communication system which eliminates cumulative jitter is comprised of an input port on which a continuous input stream of data bits is received at a transmitter input bit rate. Also, the transmitter includes an output terminal on which a continuous output series of bits are transmitted, at a transmitter output bit rate that is faster than and independent of the transmitter input bit rate. This output series of bits consists of the input stream of data bits partitioned into spaced apart data blocks, with a respective output header inserted before each block.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: December 2, 1997
    Assignee: Unisys Corporation
    Inventor: Charles Bert Hickman
  • Patent number: 5689531
    Abstract: An electronic receiver for a digital communication system which eliminates cumulative jitter is comprised of an input circuit which receives a continuous series of bits, on an input terminal, at a receiver input bit rate. This series of bits consists of data bits in spaced apart data blocks, with respective headers that have a variable length and fill the space between the data blocks. Also, the receiver includes an output circuit, which is coupled to the input circuit. This output circuit sends selected bits from the data blocks, but not from the headers, to an output port at a receiver output bit rate which is slower than the receiver input bit rate. Further, the output circuit includes a closed loop feedback control circuit, which selects the receiver output bit rate, such that it is substantially constant and such that the selected bits from the data blocks occur on the output port as a continuous bit stream.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: November 18, 1997
    Assignee: Unisys Corporation
    Inventor: Charles Bert Hickman
  • Patent number: 5686341
    Abstract: A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consist essentially of Germanium, having a crystalline grain size which is smaller than polycrystalline; and the Germanium switches from a high resistance to a low resistance upon the application of a threshold voltage across the conductors.
    Type: Grant
    Filed: November 27, 1995
    Date of Patent: November 11, 1997
    Assignee: Unisys Corporation
    Inventor: Bruce Boyd Roesner
  • Patent number: 5680416
    Abstract: A communication system which eliminates cumulative jitter is comprised of a transmitter which receives a continuous input stream of data bits at a transmitter input bit rate on an input port, and which simultaneously transmits the data bits in spaced-apart bit-serial data blocks with respective bit-serial headers that have a variable length and fill the space between the data blocks. Also, the communication system includes a receiver, coupled to the transmitter, which receives the spaced-apart data blocks, and which simultaneously generates from selected bits in the received data blocks but not the headers, an output stream of the data bits at a receiver output bit rate on an output port.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: October 21, 1997
    Assignee: Unisys Corporation
    Inventor: Charles Bert Hickman
  • Patent number: 5680415
    Abstract: An electronic repeater for a digital communication system which eliminates cumulative jitter is comprised of an input terminal on which a continuous input series of bits is received, at a repeater input bit rate. This input series of bits constitute an interleaved bit-serial sequence of input headers and data blocks. Also, the repeater includes an output terminal on which a continuous output series of bits are transmitted, at a repeater output bit rate that is not equal to and is independent of the repeater input bit rate. This output series of bits constitute an interleaved bit-serial sequence of output headers and the received data blocks.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: October 21, 1997
    Assignee: Unisys Corporation
    Inventor: Charles Bert Hickman
  • Patent number: 5673415
    Abstract: In accordance with the present invention, a high speed two-part storage interface unit includes--1) a primary I/O port (input/output port) that couples to a plurality of data processing modules; 2) a secondary I/O port that couples to a main memory module, 3) input circuits for receiving three types of write commands and one type of read command from the data processing modules, 4) several write execution modules which are serially-coupled to a time-shared memory, and 5) a control circuit by which the write commands and read commands are performed.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: September 30, 1997
    Assignee: Unisys Corporation
    Inventors: Kha Nguyen, Theodore Curt White, Bruce Edward Moolenaar
  • Patent number: 5671296
    Abstract: A first set of input index signals represents a row-column array of quantized pixels; and each input index signal in the first set represents a rectangular non-overlapping quantized pixel group which is aligned to a particular row and a particular column. By repeatedly performing three steps on different pairs of the input index signals in the first set, a second set of index signals is generated wherein a respective index signal exists for each individual pixel in the array and by which the image can be filtered. These three steps are: 1) selecting a pair of input index signals in the first set such that the two quantized pixel groups which the selected index signals represent are adjacent to each other in the array; 2) forming an address signal by combining the two selected input index signals; and 3) reading a memory with the address signal to thereby obtain an output index signal.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: September 23, 1997
    Assignee: Unisys Corporation
    Inventors: Roger William Call, Dennis Carl Pulsipher
  • Patent number: 5666515
    Abstract: Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: September 9, 1997
    Assignee: Unisys Corporation
    Inventors: Theodore Curt White, Jayesh Vrajlal Sheth, Kha Nguyen, Dan Trong Tran
  • Patent number: 5658831
    Abstract: An integrated circuit package includes an integrated circuit chip, a substrate which holds the chip, and a heat conduction mechanism which provides a path for conducting heat from the chip to a fluid medium; wherein the heat conduction mechanism is characterized as having a pressed joint which is comprised of: 1) a member that is made primarily of aluminum or copper, having a solid polysiloxane coating of less than 200.ANG. thickness, and 2) a liquid metal alloy in contact with the coating. This solid coating, on the aluminum or copper member, is fabricated without any expensive equipment by the steps of: 1) forming a liquid coating of a polysiloxane solution on the aluminum or copper member; and 2) baking that member with its liquid coating at temperatures of 100.degree. C.-300.degree. C. for 0.5 hours-3.0 hours. Thereafter the integrated circuit package is completed by placing the member with its solid coat in the heat conducting path such that a liquid metal alloy is in contact with the solid coat.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 19, 1997
    Assignee: Unisys Corporation
    Inventors: Wilber Terry Layton, Blanquita Ortega Morange, Angela Marie Torres, James Andrew Roecker
  • Patent number: 5659686
    Abstract: In a parallel processor, a plurality of data processing nodes are intercoupled through an array of message routing circuits. Each message routing circuit has multiple input channels on which messages are received and multiple output channels on which messages are sent. A message on an input channel of any one particular message routing circuit contains a header followed by data with the header consisting of a sequence of control characters which route the data. Depending on the control character sequence that is received on an input channel, the data is sent to one, two, or three output channels and each such data transmission is preceded by a respective modified header which is generated from the header on the input channel. By sequentially performing this message processing in a series of message routing circuits, the data is delivered to multiple nodes along a tree-shaped path.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: August 19, 1997
    Assignee: Unisys Corporation
    Inventor: ChiYeh Hou
  • Patent number: 5651028
    Abstract: An electronic data transmission system has a low peak-to-average power ratio by including a transmitter circuit which receives an input signal and in response generates a distorted output signal. This distorted output signal is generated such the output signal has a large magnitude when the input signal has a high probability of occurrence, and the output signal has a small magnitude when the input signal has a low probability of occurrence. The distorted output signal travels over a communication channel to a receiver circuit which regenerates the input signal by amplifying the distorted output signal with a gain that is the inverse of the gain by which the distorted signal is generated.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: July 22, 1997
    Assignee: Unisys Corporation
    Inventors: Johnny Michael Harris, Thomas Robert Giallorenzi, David William Matolak, Dan Michael Griffin