Abstract: A method and apparatus for measuring an absolute profile of a flat using an interferometer system that includes an interferometer adapted to support two flats, a detection system, and a computer adapted to compute the OPD (optical path difference) between surface of the two flats, wherein a first flat A! having a first surface and a second flat B! having a second surface are supported in the interferometer, with the second surface facing the first surface. The interferometer system measures the OPDs between the first and second surfaces for each pixel. The first flat A! then is rotated by a number of predetermined angles relative to its initial position and each time the OPDs are measured. The first flat A! is rotated to its initial position or 180.degree. therefrom. A third flat C! having a third surface is substituted for the second flat. The OPDs between the first and third surfaces are measured.

Abstract: The invention provides a technique for eliminating "ripple" or ghost fringes from a wavefront transmitted by an optical window with a very small wedge angle, distortions in the wavefront being measured by an interferometer. A collimated beam produced by the interferometer is transmitted through the optical window, which is tilted so as to prevent direct reflections from entering a detector of the interferometer. The beam transmitted through the window is reflected by a return flat back through the window and transmitted to the detector. The return flat is tilted slightly in the direction of or opposite to the direction of tilt of the window, causing the re-incident angle of the returned ray to be different from the original incident angle of the collimated beam. This causes the multiple reflections within the window to be different and to be out of phase. The ghost fringes are cancelled by appropriately tilting the return flat.

Abstract: A method of profiling a rough surface of an object includes moving the object along a z axis so that a highest point of the rough surface is optically aligned with and outside of the focus range of a solid-state imaging array. An interferogram of the rough surface then is produced by means of a two beam interferometer. The solid-state imaging array is operated to scan the rough surface along x and y axes to produce intensity data for each pixel of the solid-state imaging array for a plurality of frames each shifted from the other by a preselected phase difference. The modulation for each pixel is computed from the intensity data. The most recently computed modulation of each pixel is compared with a stored prior value of modulation of that pixel. The prior value is replaced with the most recently computed value if the most recently computed value is greater.

Abstract: A method and system are described for performing phase unwrapping integrations in a phase-shifting interferometric profiling operation. The disclosed technique uses one characteristic of modulation or slope distributions to segment the modulation or slope histogram into a plurality of sections. The principal phase values are divided into a plurality of groups in accordance with corresponding modulation or slope histogram sections. The phase unwrapping integrations are performed in such an order that the areas with a high probability of containing a 2.pi. discontinuity are contained in the last group integrated. Thus, inaccuracies due to 2.pi. discontinuities do not "propagate" to earlier-computed phase values computed by the phase unwrapping algorithm.

Abstract: A scanning probe microscope achieves increased resolution and speed in profiling a surface of a sample by producing an error signal representing a difference between a probe signal and a desired value of the probe signal. The error signal is compensated for delay in response of a position translator. The position translator moves in response to the compensated error signal to produce a change in the probe signal dependent upon how closely the probe moves along the sample surface. A signal representing height of the sample surface is produced by filtering and scaling the probe signal and summing the resulting signal with the compensated error signal. Both high frequency components of the probe signal and low frequency components of the compensated error signal are included in the sample surface height-representing signal, resulting in very high image resolution without sacrificing scanning speed.

Abstract: A scanning probe microscope includes a base, an inner piezoelectric tube, and an outer PMN translator arrangement including three PMN posts, with first ends of the PMN posts connected to the base. A first end of the inner piezoelectric tube is rigidly connected to second ends of the PMN posts. Inner quadrant conductors are disposed on the inner surfaces of the inner piezoelectric tube, and outer quadrant conductors are disposed on the outer surfaces of the inner piezoelectric tube. Separate x and y scan control voltage signals are applied to corresponding opposed quadrant conductors of the inner piezoelectric tube to control scanning of the free end of the inner tube in the x and y directions. A z scan control voltage is produced by a servo control circuit in response to a probe signal and applied to the PMN posts, which have negligible hysteresis. The servo control circuit refers to a look-up table to correct non-linearities of the PMN posts.

Abstract: A scanning probe microscope includes a probe support carrying a scanning probe, a piezoelectric transducer having a free end connected to a stage on which the sample is supported, probe sensing circuitry connected to sense a signal indicating interaction between the tip of the probe and a point of the sample surface and producing in response thereto a Z control voltage so as to optimize the interaction and produce a Z coordinate representing the height of a presently scanned point of the sample surface. Optical sensing circuitry includes a light source connected in fixed relation to the sample stage, a position sensitive photodetector, and optics focusing lens for focusing a portion of the light onto a position sensitive detector to cause it to produce X and Y position signals. The light source includes a retroreflector attached to the piezoelectric transducer receiving a beam from a stationary laser and focused by a stationary lens onto the position sensitive detector.

Abstract: A scanning probe microscope includes a base, an inner piezoelectric tube, and an outer piezoelectric tube, with a first end of the outer piezoelectric tube connected to the base. A first end of the inner piezoelectric tube is rigidly connected to a second end of the outer piezoelectric tube. Thin inner conductors are disposed on the inner surfaces of the inner piezoelectric tube and the outer piezoelectric tube, and quadrant conductors are disposed on the outer surfaces of the inner piezoelectric tube and the outer piezoelectric tube. Separate x, y, and z scan control voltage signals are applied to various quadrant conductors of the inner and outer piezoelectric tubes to control scanning of the free end of the inner tube in the x, y, and z directions, respectively.

Abstract: A method of profiling a rough surface of an object includes moving the object along a z axis so that a highest point of the rough surface is optically aligned with and outside of the focus range of a solid-state imaging array. An interferogram of the rough surface then is produced by means of a two beam interferometer. The solid-state imaging array is operated to scan the rough surface along x and y axes to produce intensity data for each pixel of the solid-state imaging array for a plurality of frames each shifted from the other by a preselected phase difference. The modulation for each pixel is computed from the intensity data. The most recently computed modulation of each pixel is compared with a stored prior value of modulation of that pixel. The prior value is replaced with the most recently computed value if the most recently computed value is greater.

Abstract: A dual SIP package for encapsulating a plurality of semiconductor die includes a first group of elongated metal leads each having first and second end portions, and a first group of enlarged metal pads each attached to the first end portion of one of the leads of the first group, a second group of elongated metal leads each having first and second end portions, and a second group of enlarged metal pads each attached to the first end portion of one of the leads of the second group, each of the pads of the first group being parallel to and aligned with a corresponding pad of the second group to form a pair. The first end portion of each of the leads of the first group is parallel to and aligned with the first end portion of a lead of the second group. Each of the die is disposed between and connected to a pair of the pads. The bottom electrode of each die is attached to a pad of the first group, and the top electrode of each die is attached to a pad of the second group.

Abstract: A motorcycle sidecar securely accommodates a handicapped driver seated in a wheelchair. Handlebars are mounted directly in front of the driver for steering the motorcycle. Other controls, including a throttle, a front brake lever, and a clutch lever are mounted on the handle bars. A rear brake lever and a gear shifting control are conveniently located in the sidecar for manipulation by the handicapped driver. A retractable ramp is provided for permitting the driver to roll his wheelchair into the sidecar. Brackets are provided for securely attaching the sidecar to a conventional motorcycle.

Abstract: A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. In the digital system, data transfers on the common bidirectional data bus are accomplished without the use of a memory synchronization signal so that a special signal conductor indicating when the memory is ready to transfer data is not required. This is accomplished by logic circuitry which expands a clock signal pulse which is applied to the microprocessor chip whenever a memory location is addressed which has a longer access time than is consistent with the width of the pulse ordinarily applied to the microprocessor to effect its operation.

Abstract: An MOS random access memory chip utilizes a column decode circuit scheme in which a signal derived from a chip select input of the random access memory chip is coupled to the gate of a switching device of dynamic IGFET NOR gates utilized to accomplish the column decoding function. This prevents the bit sense column selection conductor from being affected when an internal column selection clock signal is generated. This results in a substantial savings in power dissipation which would be required if it were necessary to provide circuitry to disable the internal column selection clock generator circuit during an unselected memory cycle.

Abstract: A two pin CMOS oscillator includes an improved input protection circuit which includes pairs of back-to-back diodes coupled between the input of an amplifier portion of the oscillator and the two power conductors which energize the oscillator. Provision of the back-to-back diode pairs permits use of an internal timing capacitor coupled between the output and input of the amplifier portion of the oscillator to be partially charged by an external timing resistor to a switching point of the amplifier portion of the oscillator. When the amplifier portion of the oscillator switches, the voltage at the input may be boosted or bootstrapped to voltages considerably beyond the range of voltage between the two voltage conductors. Thus, clipping of the voltage swings at the timing node of the oscillator by the protection circuit is avoided, and improved performance is achieved, especially at high frequencies.

Abstract: A solar cell package includes a plurality of solar cells within a space formed by a support member and a transparent cover member. A first conductor is positioned between the support member and the solar cells and makes electrical contact to a first surface of each of the solar cells. A second conductor is essentially coplanar with the first conductor and makes electrical contacts to a second surface of each of the solar cells. The output terminals of the solar cell package are connected to the first and second conductors. The first and second conductors are electrically isolated from each other and are also insulated from the support member and from the solar cells insulative means which is electrically insulated but thermally conductive to facilitate dissipation of thermal power dissipated in the solar cells.

Abstract: An MOS digital to analog converter on a semiconductor chip includes N digital inputs and a single analog output. The digital inputs control circuitry which switches in various combinations of 2.sup.0 +2.sup.1 +...2.sup.N-1 IGFETs with substantially similar voltage current characteristics coupled between a voltage supply conductor and an analog current output conductor. The IGFETs are arranged in N groups, each group being controlled, respectively, by one of the digital inputs. The number of IGFETs in each group is given by the expression 2.sup.n-1 where 1.ltoreq.n.ltoreq.N. A control circuit including a plurality of substantially identical diode-connected IGFETs is coupled between a constant current source and the voltage supply conductor. The voltage supply conductor provides a voltage which is gated by means of switching circuitry controlled by the digital inputs to the gate electrodes, respectively, of each of the groups of IGFETs.

Abstract: A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus. An index register for storing information to be utilized in an indexed addressing mode of operation is coupled to both the first and second sections of the address bus and to the data bus.

Abstract: Charge is stored on the gate of a gate controlled diode in a memory element to provide a junction breakdown memory cell. A quantity of charge representative of a logical 1 or a logical 0 may be dynamically stored in one embodiment. In another embodiment a composite silicon nitride/silicon dioxide dielectric is utilized to provide non-volatile storage of a logic state. Selection and sensing circuitry are coupled to an array of junction breakdown memory elements. Sensing circuitry detects the difference in reverse current of the gate controlled diode corresponding to a stored logical 1 and a stored logical 0, respectively.

Abstract: Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. The input is coupled to circuitry which inhibits loading of the next instruction to be executed in response to an interrupt request signal applied to the interrupt request input, and also forces a code into the instruction register in response to the interrupt request signal. The code is substantially similar to the code for a software wait instruction or a software interrupt instruction. Therefore, much of the same circuitry within the microprocessor can be used for executing an interrupt operation, a software wait instruction, or a software interrupt instruction.

Abstract: A method of generating addresses in a microprocessor includes steps of storing first informationrepresentative of a first address in a first register, such as a program counter register. The first information is transmitted to a first address bus in order to effect addressing the contents of a first location represented by the first address. The first information is also transmitted via the address bus to an incrementor-decrementor circuit. The first information is incremented to produce second information representative of the address of the next instruction during the addressing of the first location. The second information is then transmitted to the first register.