Abstract: A zener diode and resistor network is coupled to a single conductor by a switching device which, in combination with the network, produces a voltage on the conductor representative of one of four commands selected by the switching device. Another zener diode and resistor network is coupled to the receiving end of the transmission conductor and operates to generate two ternary signals which, in combination, are representative of the selected command. A plurality of dual-threshold CMOS logic gates generates four binary output signals responsive to the two ternary signals.

Abstract: A processor including a first bus, a second bus, and a control circuit for producing control signals includes a counter having a plurality of inputs and outputs responsive to the control circuit and coupled between the first and second buses for incrementing digital information present at the inputs of the counter. The processor includes a first coupling circuit responsive to the control circuit for coupling the counter inputs to the first bus to effect transferring digital information from the first bus to the counter inputs. A second coupling circuit couples the counter inputs to the second bus to transfer digital information from the second bus to the counter inputs in response to the control circuit. A third coupling circuit couples the counter outputs to the second bus to transfer digital information from the counter output to the second bus.

Abstract: An N-bit binary address decoder suitable for use in an emitter-coupled logic bipolar random access memory (RAM) is provided. Each of the N address input signals is applied to an input terminal and is level shifted and applied to the input node of an emitter-coupled logic inverter. The outputs of the emitter-coupled logic inverter are the collectors of the emitter-coupled transistors on which complementary output signals representative of the corresponding binary address input signal are produced. The complementary output signals generated by the N inverters are connected to 2.sup.N AND gates to form the possible 2.sup.N minterm combinations. Each of the AND gates includes a load resistor coupled to a power supply and N Schottky diodes having their anodes coupled to the load resistor and their cathodes coupled to the corresponding address inverter output terminals.

Abstract: A four-IGFET memory cell is utilized as a static (or DC) memory cell rather than as a dynamic memory cell. When the memory cell is in the standby mode an intermediate voltage is applied to a selection conductor coupled to the gates of the gating IGFETS of the memory cell. The intermediate voltage applied to the "X" selection conductor under standby conditions is slightly in excess of two IGFET threshold voltages, and is sufficient to maintain the stored logical state, yet causes very little power to be dissipated by the memory cell. A full logical "1" level is applied to the selection conductor during either a read operation or a write operation if the memory cell is selected, i.e. is addressed by the decoding circuitry in response to chip select and address inputs of a memory chip incorporating the memory cell. If the memory cell is unselected during a read or write operation, a logical "0" is applied to the selection conductor.

Abstract: An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.

Abstract: An output circuit including a latch circuit and a push-pull output driver driven by the latch circuit is controlled by disable circuit which disables the output circuit when a random access memory semiconductor chip on which the output circuit is located undergoes an unselected memory cycle, i.e., is unselected. The disable circuit includes a bootstrap NOR gate having a series power switching IGFET coupling its load device to a voltage supply conductor. The power switching IGFET is controlled by the output of the disable circuit so that the disable circuit shuts off its own power at the same time it disables the output latch when the random access memory chip undergoes an unselected memory cycle. Essentially, the disable circuit operates in such a manner that it shuts off its own power and also disables the output circuit in response to a second input signal, conditioned on the occurrence of an earlier first signal.

Abstract: A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus.

Abstract: A floating base transistor connected within an integrated circuit to provide a high temperature high voltage low current bypass device having the same type of temperature dependence as the leakage current shunted therethrough. The bypass device is connected to provide its I.sub.CEO current as a current source through which a parasitic leakage current is diverted which would otherwise produce a base current of an output transistor which is supposed to be in the off condition. The parasitic leakage current includes the I.sub.CEO current of an opposite polarity driving transistor in the off condition having its emitter connected to a power supply and its base connected to an input circuit and its collector connected to the base of the output transistor. In one embodiment the floating base transistor is a PNP substrate transistor having its collector connected to ground, its emitter connected to the base of an NPN output transistor, and its base floating.

Abstract: A decoder for a semiconductor MOS random access memory includes a dynamic NOR gate having a first output. The decoder also includes a selection MOSFET for providing a selection signal to a selection conductor connected to a row or column of an array of storage cells of said random access memory. The gate electrode of the selection MOSFET is connected to the output node of the NOR gate. The drain of the selection MOSFET is connected to a signal conductor adapted to having a signal applied thereto which is a function of a read/write signal applied to said random access memory. The source of the selection MOSFET is connected to the selection conductor. A feedback MOSFET is coupled between the output of the dynamic NOR gate and the selection conductor and has its gate electrode controlled by the signal which is a function of the read/write input signal. When the NOR gate is selected by a particular combination of address input variables, its initially precharged output node is discharged to ground.

Abstract: Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

Abstract: An MOS (Metal-Oxide-Semiconductor) integrated circuit includes four dedicated registers thereon, two of which are "write only" registers having the capability of being written into, but not read from, by means of buffer circuitry for coupling a bidirectional data bus to the dedicated registers. The other two dedicated registers are "read only" registers having the capability of being read from, but not written into, by means of the buffer circuitry. The integrated circuit chip is itself addressable by means of a plurality of address conductors of an address bus coupleable to the integrated circuit chip, and the four dedicated registers within the integrated circuit chip are further addressable by means of an additional address conductor called a register select address line.

Abstract: A complementary field effect transistor integrated circuit includes an input buffer, internal high density logic circuitry having a collapsed guard ring structure associated therewith, an internal power source which provides operating voltage for the internal high density logic lower than the junction reverse breakdown voltage of the collapsed guard ring structure, and an output level shifter circuit. The output level shifter circuit and input buffer, and internal power source have a conventional non-collapsed guard ring structure associated therewith.

Abstract: An overvoltage protection circuit in an integrated circuit for increasing the breakdown voltage of the integrated circuit between first and second terminals thereof. Diode-connected transistors are connected in series between the first terminal and a resistor. The resistor is connected to the base of a first transistor having its emitter connected to the second terminal and its collector connected to the base of a second transistor having its emitter connected to the second terminal and its collector connected to the first terminal. If an overvoltage applied between the first and second terminals exceeds the sum of the emitter-base reverse breakdown voltages of the diode-connected transistors, current flows into the base of the first transistor, causing it to saturate, thereby preventing the emitter-base junction of the second transistor from being forward biased. The collector to emitter breakdown voltage of the second transistor is thereby increased.

Abstract: A program register is coupled between a data bus N bits wide and an address bus N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. For certain instructions, the address bus is utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter, depending on the type of instruction being executed.

Abstract: A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and a storage node of one of the dummy storage cells of each row of storage cells. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected. Charge initially stored in the selected storage cell is redistributed on the opposite sense-write conductor and is subsequently amplified by the sense amplifier, and produced in inverted amplified form at the storage node of the dummy storage cell.

Abstract: A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. The digital system uses a multi-level interrupt circuit arrangement including a masked interrupt request input responsive to a multi-plexed interrupt request from peripheral circuits of the system and a non-masked interrupt request input which activates circuitry internal to the microprocessor chip for bypassing program control in initiating an interrupt sequence.

Abstract: A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and one of the regenerative sense amplifiers for each of the rows, respectively. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected after redistribution of charge initially stored in the selected storage cell onto the sense-write conductor takes place. The sense voltage resulting from the charge redistributed on the opposite sense-write conductor is subsequently amplified by the sense amplifier, and provided in inverted and noninverted form on the two respective sense-write conductors.

Abstract: Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

Abstract: The chip architecture of an MOS microprocessor chip includes data bus input-output buffer circuitry located along the lower right hand edge of the chip. High order address buffer output circuitry is located along the bottom of the chip. Directly to the left of the data bus input-output buffer circuitry is the arithmetic logic unit circuitry, and to the right of this and adjacent to the high order address bit buffer circuitry is located a register section including first accumulator register, a second accumulator register, high and low order index registers, a high order incrementer and an associated program counter, a low order incrementer and associated program counter, a high order stack pointer register and a low order stack pointer register, and a temporary register arranged on the surface of the microprocessor chip in a particular sequence. To the left of the register section and along the lower left hand edge of the chip is located a plurality of low order address bit buffer circuits.

Abstract: A voltage level sustaining circuit for an IGFET driver circuit having an output node includes a first IGFET coupled between a voltage supply conductor and an output node of a driver circuit. The gate of the first IGFET is coupled to a source of a second IGFET having its gate and drain connected to the voltage supply conductor. A boosting capacitor is connected between the gate of the first IGFET and a conductor to which a refresh pulse is applied. The refresh pulse need be applied only often enough and be of sufficient magnitude to turn on the first IGFET sufficiently hard that the output node is held at the voltage of the voltage supply conductor.