Abstract: A multilayer, high yield and high density integrated circuit (IC) chips interposer and the method of manufacture therefore. A thin polyimide film is circuitized with copper on both sides. One side may be reserved for power or ground with the opposite side being a signal plane. Adhesive is laminated over both sides covering the circuit patterns. Vias are drilled through at least one adhesive surface, and through the polyimide film. Metal (copper) is blanket sputtered to coat the via walls. Polymer Metal Conductive (PMC) paste is screened to at least partially fill the vias. The Blanket metal is sub-etched using the screened PMC as a mask. Layers are stacked to form the interposer with the PMC bonding the stacked layers together and electrically interconnecting between layers.

Abstract: Method of fabricating a vertical Metal Oxide Semiconductor Heterojunction Field Effect Transistor (MOSHFET) which is in a layered wafer made by successively growing an N.sup.+ silicon layer, and a N.sup.- silicon layer, a P.sup.- Si.sub.1-x Gex layer, a P.sup.- Silicon layer and then, an N.sup.- silicon layer, one on top of the other. Trenches are etched through the top 3 layers to form islands that are the MOSHFETs heterojunction channel. A gate deposited or grown in a trench extends vertically from the drain at the bottom of the trench to the source in the layer near the top of the trench.

Abstract: A method of replacing IC chip package wiring having an interposer comprising removing an interposer having a plurality of adhesively laminated interposer layers from the package, delaminating and replacing at least one interposer layer with a corrected interposer layer, relaminating the interposer layers with adhesive thus producing a replacement interposer and remounting the replacement interposer to the IC chip package.

Abstract: A Conductor Insulator Semiconductor (CIS) heterojunction transistor. The CIS transistor is on silicon (Si) substrate. A layer of n type Si is deposited on the substrate. A trench is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO.sub.2. A layer of p type Si.sub.1-z Ge.sub.z (where z is the mole fraction of Ge and 0.1.ltoreq.z.ltoreq.0.9) is deposited on the n type Si layer. A p.sup.+ base contact region is defined in the p type Si.sub.1-z Ge.sub.z region above the oxide filled trench. A n type dopant is ion implanted into both the Si.sub.1-z Ge.sub.z and n Si layers and may extend slightly into the substrate, forming a collector region. A thin oxide layer is deposited on the Si.sub.1-z Ge.sub.z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter. Alternatively, the emitter may be p.sup.+ polysilicon.

Abstract: This field-effect transistor comprises a conductive substrate (2) serving as the gate electrode, an insulating barrier layer (3), and a superconducting channel layer (1) on top of the barrier layer (3). The superconductor layer (1) carries a pair of mutually spaced electrodes (4, 5) forming source and drain, respectively. The substrate is provided with an appropriate gate contact (6).The substrate (2) consists of a material belonging to the same crystallographic family as the barrier layer (3). In a preferred embodiment, the substrate (2) is niobium-doped strontium titanate, the barrier layer (3) is undoped strontium titanate, and the superconductor (1) is a thin film of a material having a lattice constant at least approximately similar to the one of the materials of the substrate (2) and barrier (3) layers. A preferred material of this type is YBa.sub.2 Cu.sub.3 O.sub.7-.delta., where 0.ltoreq..delta..ltoreq.0.5.

Abstract: A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al.sub.2 O.sub.3. The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof.

Abstract: Spin coating of resist on a semiconductor wafer is done in a controlled chamber, starting with introducing a resist solvent vapor into the chamber from a nozzle or an adjacent chamber, applying the resist by spraying a very thin layer of the resist material and then removing solvent from the chamber. The result is a saving in resist material and enhanced coating uniformity.

Abstract: This field-effect transistor comprises a conductive substrate (2) serving as the gate electrode, an insulating barrier layer (3), and a superconducting channel layer (1) on top of the barrier layer (3). The superconductor layer (1) carries a pair of mutually spaced electrodes (4, 5) forming source and drain, respectively. The substrate is provided with an appropriate gate contact (6).The substrate (2) consists of a material belonging to the same crystallographic family as the barrier layer (3). In a preferred embodiment, the substrate (2) is niobium-doped strontium titanate, the barrier layer (3) is undoped strontium titanate, and the superconductor (1) is a thin film of a material having a lattice constant at least approximately similar to the one of the materials of the substrate (2) and barrier (3) layers. A preferred material of this type is YBa.sub.2 Cu.sub.3 O.sub.7-.delta., where 0.ltoreq..delta..ltoreq.0.5.

Abstract: Switchable diffused junction capacitors providing selectable data signal paths in a logic gate. A control circuit, such as a current switch, renders one of the junction capacitors conductive to present a large diffusion capacitance which acts as a fast signal pathway to the respectively applied data signal. Non-conducting junction capacitor presents a negligible diffusion capacitance which essentially acts as an open circuit to the respectively applied data signal. The control circuit response is slow and non-critical. The combination of a slow response control to configure selectable fast response data signal pathways is useful in "half good" or "partial good" semiconductor chip technologies, data buffers with fast flush, and self-test, self-repair chip designs, among others.

Abstract: A Double Heterojunction Bipolar Transistor (DHBT) and the method of fabrication therefor. First a layered wafer is prepared on a semi-insulating GaAs substrate. The bottom wafer layer is n.sup.+ GaAs, followed by n.sub.- AlGaAs, a thin layer of n AlGaAs (which form the DHBT's collector) and a base layer of p.sup.+ GaAS. A layered plug fills a trench etched in the base layer. The bottom two plug layers are AlGaAs and the top plug layer is GaAs. Next, an emitter is ion-implanted into the plug core and an extrinsic base region is ion-implanted. Finally, base, emitter and collector contacts are formed.

Abstract: A database management system for use in designing integrated circuit chips. A large number of designers and users are given concurrent access to design data stored in a Master Table by providing each designer with a private copy of the Master Table called the designer's Virtual Table. Each designer can independently alter data displayed from the designer's Virtual Table without interfering with other designers. Whenever a designer alters the displayed data, the displayed row containing the altered data is written to the Master Table and the designer's Virtual Table, provided that the Master Table row's time-date stamp matches the corresponding Virtual Table row's time-date stamp. If the time-date stamps do not match, then the Master Table row is copied into the Virtual Table, the designer receives an error message, and the designer is allowed to update the corrected row.

Abstract: A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate. The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has: A first region of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint; a second region extending from the first region to the FET's drain, comprised of a superlattice of alternating Si and SiGe layers; and, a third region of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.

Abstract: A bit decoder for a memory array includes a decode NOR/OR circuit coupled to an output driver circuit. The decode NOR/OR circuit includes a plurality of input signals connected to respective input FET's all of which are connected in parallel between a common source and a common drain node. One input is also connected to an active pullup FET which is connected in series with the input FET's at the common drain node and which is always maintained slightly on. A bipolar transistor pulls down the common drain node and a bleeder FET pulls down the common source node. The output driver is a BICMOS circuit that provides both the bit selection and bit refresh signals which are of opposite phase.

Abstract: A more efficient method of macro placement and graying for electron beam (e-beam) lithography. The e-beam field is divided into smaller subfields. Repetitious shapes or collections of shapes which are repetitious are represented by macros. Some shapes span or are intersected by subfield boundaries. After the shapes are converted to fill rectangles and the fill rectangles are proximity corrected, the macro containing the proximity corrected fill rectangles is grayed and placed without being unnested. First, the Macro Organization Step, the macro's fill rectangles are sorted. Tall-narrow macros are sorted top to bottom then left to right, short-wide macros are sorted left to right then top to bottom. After the sort, chains of rectangles are created and a shadow is generated for the macro and for each chain. Next, the Macro Placement and Graying Step, a determination is made of whether and where macro graying will be required.

Abstract: A balancing circuit which may be used as part of a random access memory system for eliminating bit line offset, is disclosed. The balancing circuit contemplated by the invention is capable of supporting rapid memory accesses (such as reads when the memory enters a "read" mode); and simultaneously minimizes the potential for the disturbance of data stored in the memory cells attached to a given bit line pair when the memory is in a "standby" mode following deselect. The invention is particularly useful in connection with the Harper/PNP memory cell arrays.

Abstract: A system and method for exposing a radiation sensitive layer to one or more repetitious design cells. Each design cell includes at least one design shape on at least one buildlevel. Each shape represents a circuit shape, or part of a circuit shape on an integrated circuit layer in a circuit on an integrated circuit chip. For each buildlevel: the design is parceled into units that contain approximately the same optimum number of vertices; and for each parcel: Each design cell occurrence, or transform, is examined to determine whether it has proximity effect commonality with other cell transforms (a common environment) and, based on that determination, the cell transform is placed into one of three groups, Macro Candidates, Nested Candidates, and Unnested Candidates. In each Macro Candidate and Nested Candidate any overlapping shapes are combined, or unioned, to form a single shape and, then, the shapes are reconstructed (filled) with rectangles (fill rectangles).

Abstract: This field-effect transistor comprises a conductive substrate (2) serving as the gate electrode, an insulating barrier layer (3), and a superconducting channel layer (1) on top of the barrier layer (3). The superconductor layer (1) carries a pair of mutually spaced electrodes (4, 5) forming source and drain, respectively. The substrate is provided with an appropriate gate contact (6).The substrate (2) consists of a material belonging to the same crystallographic family as the barrier layer (3). In a preferred embodiment, the substrate (2) is niobium-doped strontium titanate, the barrier layer (3) is undoped strontium titanate, and the superconductor (1) is a thin film of a material having a lattice constant at least approximately similar to the one of the materials of the substrate (2) and barrier (3) layers. A preferred material of this type is YBa.sub.2 Cu.sub.3 O.sub.7-.delta., where 0 .cent..delta..ltoreq.0.5.

Abstract: A method and apparatus is provided for estimating the centerline of an alignment/overlay measurement target by means of projecting light from a tunable, variable wavelength the illumination source onto the target, then performing optical observation of the measurement mark and providing an output signal representing the quantity measured in the observation, computing from the output signal a criterion of signal asymmetry to provide an output product, and tuning the tunable illumination source as a function of the output product. As a result tuning adjustment of the wavelength of illumination is employed to expose an observed feature, and the illumination source is tuned until the criterion is minimized, thus improving the accuracy of the estimated centerline.

Abstract: A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to both load transistors, are connected to a drain line. The word line is connected to an emitter common to both of the load transistors. The cell is connected to a bit line pair through Schottky Barrier Diodes (SBD's) or, alternatively, through emitters of transistors which share a common base and a common collector with the cross coupled storage transistors.

Abstract: A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formedthereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .