Abstract: A method of language recognition wherein decoding ambiguities are identified and at least partially resolved intermediate to the language decoding procedures to reduce the subsequent number of final decoding alternatives. The user is questioned about identified decoding ambiguities as they are being decoded. There are two language decoding levels: fast match and detailed match. During the fast match decoding level a large potential candidate list is generated, very quickly. Then, during the more comprehensive (and slower) detailed match decoding level, the fast match candidate list is applied to the ambiguity to reduce the potential selections for final recognition. During the detailed match decoding level a unique candidate is selected for decoding. Decoding may be interactive and, as each ambiguity is encountered, recognition suspended to present questions to the user that will discriminate between potential response classes.

Abstract: A liquid crystal display element. The liquid crystal display includes a first substrate 3, a second substrate 4 paired with the first substrate 3, a liquid crystal layer 5 interposed between the first substrate 3 and the second substrate 4, and a switching electrode comprising a first comb-shaped electrode 1 and a second comb-shaped electrode 2. Preferably, a first domain 6 and a second domain 7, which are preferably symmetrically polarized about a center line X between opposing electrodes, are formed between a tooth 1-1 of the first comb-shaped electrode 1 and a tooth 2-1 of the second comb-shaped electrode 2 constituting the opposing electrodes of the switching electrode.

Abstract: An occlusion culling method for image processing and system therefor. The culling method first determines which polygons are hidden, or occluded, by other objects. These hidden or occluded polygons will not contribute to the final scene and, therefore, need not be rendered. In the first major step, the input models are preprocessed to build a hierarchical data structure which is as an approximation to the input models. Simple polygonal occluders are determined for substitution in place of the complex image geometry in successive visibility queries. Once the first preprocessing step is complete, the second step may be executed at run-time, while a user is inspecting, or visualizing, the input. In the second step, the occluders, determined in the first step, are used to selectively forego rendering shapes or shape portions that are unseen from the current viewpoint.

Abstract: This invention provides methods and apparatus for a special object such as a handicapped individual and/or special equipment with access to and from telecommunications and computer controlled equipment. The equipment being such as to let it be known of the special object being in a particular moving or still environ, and requiring special attention from and/or by others entering or located in that environs The special object, handicapped person or special equipment is made known to those in the environ so as to protect/preserve/serve that object, individual, special equipment, and/or to others entering or located in that environ. The equipment transmits an alarm type signal that a handicapped individual or special equipment is in the environ. The computerized apparatus/method being adapted to be responsive to particular sensations, seeing, hearing, feeling, smelling, etc., which are operational in the particular handicapped individual.

Abstract: A method of manufacturing a color liquid crystal display element. The method includes the steps of: forming coloring layers composed of a plurality of colors on a transparent substrate on which a thin film transistor structure, a gate line and a data line are formed; forming a transparent conductive film over the entire transparent substrate on which the coloring layers are formed; coating the entire surface of the transparent conductive film with a negative resist; exposing the negative resist to a light using the gate line and the data line as a photomask, the light being emitted from a light source facing a back side of the transparent substrate, the light substantially having wavelength bands excluding 390 nm to 440 nm; developing and baking the exposed negative resist; and etching and removing the transparent conductive film in a portion where the negative resist is removed.

Abstract: A system, apparatus and method for generating a transparent window on an application window designated by an operator. An annotation is drawn in the transparent window depending on the kind of message generated on the transparent window. The invention can be utilized in collaborating with another terminal located in a remote location. There are a scheme in which a window of an application to be collaborated and a transparent window corresponding thereto are started in the both systems and only the data such as an image drawn on the transparent window is transmitted to the collaborating system and another scheme in which an application to be collaborated is run only on one of the systems and an image merging the annotation data is transmitted to the other system.

Abstract: An emergency backup system, method and computer program product for backing up data on one or more computers located in an identified danger zone. When an emergency occurs, computers in the danger zone are connected to a network. The computers may be distributed at various remote locations. The protected locations each include a sensor for sensing an emergency situation and signaling the local computer of an impending emergency. The sensor also signals remote computers of the occurrence of the emergency. The computers may have been connected together over a network or, upon receiving an emergency signal, may connect together into a backup network. Local computers in the danger zone are connected across the network to remote computers with sufficient available storage to backup data from a connected local computer. The backup may be a full backup, a partial backup or a selective backup. The computers may include PCs, PDAs and servers. The network may be a LAN, a wireless network, a phone network or a WAN.

Abstract: A system and method for dramatically reducing the number of vertices defining a polygon on a grid, without significantly changing its effective enclosed area is disclosed. A smoothing process is executed on any general purpose computer system to operate on one or more representations of one or more curves. Each of the curves has a set of a plurality of vertices. The smoothing process first selects a first vertex, a third vertex, and a second middle vertex, the first, second, and third vertices being sequential but not necessarily consecutive on the curve. Then the smoothing process determines the area of a triangle formed by the first, second, and third vertices. This triangular area is compared to a threshold area. If the area is less than the threshold, new vertices are selected along the curve and the process is repeated. However if the area of the triangle is greater than or equal to the threshold, the second (middle) vertex is marked as an important vertex before a new set of vertices is selected.

Abstract: A language recognition system, method and program product for recognizing language based input from computer users on a network of connected computers. Each computer includes at least one user based language model trained for a corresponding user for automatic speech recognition, handwriting recognition, machine translation, gesture recognition or other similar actions that require interpretation of user activities. Network computer users are clustered into classes of similar users according to user similarities such as, nationality, profession, sex, age, etc. User characteristics are collected by sensors and from databases and, then, distributed over the network during user activities. Language models with similarities among similar users on the network are identified. The language models include a language model domain, with similar language models being clustered according to their domains. Language models identified as similar are modified in response to user production activities.

Abstract: A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

Abstract: An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.

Abstract: A method of forming EEPROM cells. The method includes forming a tunnel oxide layer on a wafer and forming floating gates on the tunnel oxide layer with the floating gate having sidewalls. Isolation regions may be formed adjacent the sidewalls. A conformal ONO layer of dielectric is formed on the floating gate and sidewalls, using Chemical Vapor Deposition. Next, a selective etch material layer is deposited on the wafer over the conformal dielectric layer. A polish stop layer is deposited on the wafer over the selective etch material layer to define an upper polishing surface above the floating gate. The exposed polish stop layer and underlying selective etch material are removed by depositing an oxide layer on the polish stop layer and then polishing the deposited layer coplanar with the polish stop layer which is an upper polishing surface above the floating gates.

Abstract: In a neural network of N neuron circuits, having an engaged neuron's calculated p bit wide distance between an input vector and a prototype vector and stored in the weight memory thereof, an aggregate search/sort circuit (517) of N engaged neurons' search/sort circuits. The aggregate search/sort circuit determines the minimum distance among the calculated distances. Each search/sort circuit (502-1) has p elementary search/sort units connected in series to form a column, such that the aggregate circuit is a matrix of elementary search/sort units. The distance bit signals of the same bit rank are applied to search/sort units in each row. A feedback signal is generated by ORing in an OR gate (12.1) all local search/sort output signals from the elementary search/sort units of the same row. The search process is based on identifying zeroes in the distance bit signals, from the MSB's to the LSB's. As a zero is found in a row, all the columns with a one in that row are excluded from the subsequent row search.

Abstract: A base neural semiconductor chip (10) including a neural network or unit (11(#)). The neural network (11(#)) has a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit (11) includes logic for generating local result signals of the "fire" type (F) and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip.

Abstract: Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits form a chain. The daisy chain circuit distinguishes between the two possible states of the neuron circuit (engaged or free) and identifies the first free "or ready to learn" neuron circuit in the chain, based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network having daisy chain input and output signals complementary to each other. The daisy chain circuit includes a 1-bit register (601) controlled by a store enable signal (ST) which is active at initialization or, during the learning phase when a new neuron circuit is engaged. At initialization, all the Daisy registers of the chain are forced to a first logic value.

Abstract: A cleaning apparatus for cleaning chemically processed articles between chemical processing steps. The cleaning apparatus includes a sealable pressurization vessel. After a chemical process step, an article, such as a semiconductor wafer is placed in the vessel. The vessel is sealed. Vessel pressure is adjusted. Solvent in the vessel is heated to a boil forming a vapor. Solvent vapor is recondensed by a primary condensing coil. Condensed solvent rains onto the article, washing it. After the article is clean, it is dried when a secondary condensing coil condenses the solvent vapor, causing the distilled solvent to rain into and be collected by a collection tray. Collected solvent is channelled into a storage reservoir. The storage reservoir is sealed after all of the solvent is collected. The vessel is opened to remove the cleaned article.

Abstract: A boundary independent decoder for a Synchronous Dynamic Random Access Memory (SDRAM) with an n bit burst transfer block length. A user, usually a processor or microprocessor requests access to a block of SDRAM memory. The requested block may begin between array decode boundaries. A column address is decoded by an SDRAM column decoder. The decoder selects a starting boundary for 2n bits. The first requested bit is in the first n bits of the 2n selected bits. Thus, the entire n bit block is included in the selected 2n bit block. The n bit block is selected from the selected 2n bits and latched in a high speed decoder/register in a sequentially scrambled order, i.e., the i.sup.th bit is the first requested bit and the requested bit order is i, . . . , (n-1), . . . , 0, . . . , (i-1). Latched data is scrambled either sequentially or interleaved, if required. Scrambled data is burst transferred off chip.

Abstract: A fault tolerant memory system is described including a plurality of memory chips arranged to produce an array of addressable locations. Each addressable location comprises a plurality of data bits and a plurality of check bits for checking the integrity of all the data bits and check bits at a given addressable location. A pool of spare chips including at least two spare chips are available for assignment to replace any of said memory chips or a previously assigned spare chip in the event that a chip failure is identified. Means for detecting and assigning spares, in response to the data bits and the check bits read from a given location in memory, is provided for detecting a failing memory chip or previously assigned spare chip and for assigning a previously unassigned spare chip to replace the failing memory chip or previously assigned spare chip.

Abstract: A method for removing conductive metals on a semiconductor chip while leaving a foundation on which the conductive metal is in contact with substantially intact. The foundation includes a dielectric layer and a connecting stud. The dielectric layer is formed from a material which has a relatively high reactivity to an attack by a base, but has a relatively low reactivity to an attack by acid. A first planarization process is applied to the semiconductor chip, the first planarization process attacks the conductive metal at a high rate and is discontinued prior to when the connecting stud via is exposed to direct effects of the first planarization process. A second planarization process is applied to the semiconductor chip. The second planarization process attacks the conductive metal at a relatively high rate, but attacks the connecting stud at a low rate. The second planarization process substantially removes what is left of the conductive metal after the first planarization process.

Abstract: An apparatus for measuring charge in an oxide layer overlying a silicon substrate containing very high density product chips characterized by thick oxides and high substrate doping levels in the field regions. A specially designed extremely thin conductive probe is pressed against the oxide layer whose charge is to be measured. A bias is applied to the probe for biasing the underlying silicon surface into accumulation or inversion. An intensity modulated light beam is focussed at the point of probe contact. The resulting amplitude modulated photovoltage is detected and applied to a computer to derive the value of the oxide charge therefrom.