Abstract: A packet-data FIFO buffer system comprises a FIFO buffer with a series of FIFO memory locations. Each FIFO memory location includes a data section for storing a packet data word and a flag section for storing an indication of whether or not the associated data section includes the last word of a packet. The FIFO buffer capacity is not limited to the number of maximum length packets it can hold; instead, a greater number of small packets can be stored. This increases the effectiveness of available FIFO memory and minimizes communication delays along the channels serviced by the FIFO. The FIFO design is simple and fairly self contained so that minimal external logic and control is required. In addition, an indication of the presence or absence of a complete data packet in the FIFO buffer can be easily obtained by logically adding (ORing) the contents of the flag sections.

Abstract: A "wrapped-line" direct-mapped cache is disclosed that stores words with main-memory addresses that succeed a requested address where a conventional nonwrapped direct-mapped line-unit cache would store words with main-memory addresses that precede the requested memory address. Since succeeding addresses are more likely to be called "soon" after a requested address, the wrapped-line direct-mapped cache provides more efficient use of cache capacity, and thus more effectively enhances the performance of an incorporating system. The wrapped-line direct-mapped cache has indexed storage locations. Each storage location has sections for storing a tag, a string-boundary indicator, and a line of words. Each storage location has a line index, and each word position in a line has a word-position index. To determine whether a requested address results in a hit or a miss, the match logic divides the requested address into high, intermediate, and low segments.

Abstract: A method for designing a constant multiplier system comprises identifying a repeated pattern in a minimal signed digit expression of a multiplier, designing a first accumulator stage to compute the product of a multiplicand by an instance of the pattern, and designing a second accumulator stage for accumulating shifted replicas of the pattern to yield a final product. Remainder terms, for example corresponding to non-zero digit positions not included in any instance of the pattern, are also accumulated at the second stage. By limiting the method to patterns with at least two non-zero values, the result tends to reduce the number of operations that must be performed to determine a final product. Thus, the size, complexity and speed of a constant multiplier system can be optimized.

Abstract: A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel region is recessed. A differential oxide growth then serves to mask the source and the drain for channel threshold adjust and punch-through implants. A doped polysilicon gate is formed, with the thinner area of the differential oxide serving as the gate oxide. In the resulting structure, the punch-through dopant is spaced from the source and the drain, reducing parasitic capacitance and improving transistor switching speeds.

Abstract: A constant multiplication device is designed for multiplying a received binary multiplicand by a constant multiplier which, when expressed in binary or signed-digit notation, includes a repeated pattern with three or more non-zero values. The device includes a pattern-product term generator that receives the multiplicand and generates terms corresponding to each of the non-zero values of the pattern. If, when all instances of the pattern are subtracted from the multiplier there are non-zero values in the difference, the pattern-product term generator can also generate remainder-product terms. The pattern-product terms, but not the remainder-product terms, are input to a pattern compressor that yields pattern-product partials; the compressor can be a carry-save adder and the partials can be in the form of a pseudo sum and a pseudo carry. A replica generator generates shifted replicas of each pattern-product partial. The replicas are input to a replica compressor, as are any remainder-product terms.

Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Abstract: A zero-run-length encoder for a JPEG compression system comprises an addressable memory for storing 63 input values (quantized AC DCT coefficients), zero-detection logic, a shift register, a value generator, an accumulator, a Huffman encoder, done-detection logic, and last-value-detection logic. For each input value, the zero-detection logic stores zero/nonzero indications in a respective bit position of the shift register. The value generator includes a leading-zero counter that determines the number of leading zeroes in the leading fifteen bit positions of the shift register. This count is used to determine an offset value which is added to a previous address value (initially zero) to yield a present address value. The present address value is used to select a memory location from which an input value is read from memory into the Huffman encoder. The Huffman encoder generates an output code as a function of the addressed input value and the leading zero count.

Abstract: Titanium is deposited using a low-pressure chemical-vapor deposition to provide good step coverage over an underlying integrated circuit structure. A rapid thermal anneal is performed using an ambient including diborane. The rapid thermal anneal causes the titanium to interact with underlying silicon to form titanium silicide. Concurrently, the diborane reacts with the titanium to form titanium boride. A composite barrier layer results. Aluminum is deposited and then patterned together with the composite barrier layer to define a first level metalization. Subsequent intermetal dielectrics, metalization, and passivation layers can be added to form a multi-level metal interconnect structure. The titanium boride prevents the aluminum from migrating into the silicon, while the titanium silicide lowers the contact resistivity associated with the barrier layer. The relatively close match of the thermal coefficients of expansion for titanium boride and silicon provides high thermal stability.

Abstract: A liquid level monitor uses a tube to confine a float to a vertical path with a canister containing a lower liquid and an upper liquid which meet at a liquid boundary, the level of which is to be monitored. Light from a light-emitting diode is conveyed to a vertical position of the tube by an optical fiber. A second optical fiber is arranged in a diametrically opposed position of the tube to detect light transmitted across the tube from the first optical fiber. The float is more transmissive than either liquid. When the level of the boundary falls to the level of the optical fibers, received light increases. The second optical fiber conveys this return light to a photodetector, the output of which can be used to trigger an alarm indicating that the boundary level is low.

Abstract: A purge process for an LPCVD TEOS silicon dioxide deposition method uses a series of five purge cycles to allow low-defect wafer processing with less frequent chamber removal and cleaning. The purge process begins by loading dummy wafers into the chamber. Chamber pressure is reduced to below 20 mTorr. A maximal nonreactant gas flow for two minutes is used to dislodge and carry away contaminants such as flakes from silicon dioxide previously deposited on the chamber wall. After the first four of five purge cycles, the method returns to the reduction of chamber pressure, e.g., by maintaining the vacuum on while the gas sources are turned off. After the fifth cycle, the chamber is slowly filled with nitrogen until ambient pressure is reached. Then the dummy wafers are removed. The system is then ready for processing product wafers with reduced particle counts. The purge process is benign in that it only uses equipment and procedures of the type used during product wafer processing.

Abstract: A 4.times.1 multiplexer for an electrically configurable device uses novel logic gates to logically combine outputs from two SRAM memory cells to control pass gates between the multiplexer signal inputs and a multiplexer output. Each logic gate has three transistors. A complementary NMOS/PMOS pair of transistors defines a transmission gate. The gate of the NMOS transistor defines a first logic-gate input, while the gate of the PMOS transistor defines a second logic-gate input. Their sources are coupled and cooperatively define a third logic-gate input. Their drains are coupled and cooperatively define the logic-gate output. A third transistor, with its gate tied to the third input, couples the logic-gate output to ground when the transmission gate is OFF. The first and second logic-gate inputs are respectively coupled to complementary outputs of one memory cell, while the third logic gate input is coupled to an output of the other memory cell.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. For each NMOS transistor, a polysilicon NMOS gate lead structure includes three sections: a heavily doped gate section, an undoped resistor section, and a heavily doped contact section. The heavily doped contact section is contacted by a metal delivering a logic low voltage (V.sub.SS) so that the NMOS gate is resistively coupled to V.sub.SS. This resistance cooperates with the gate to drain resistance to define a voltage divider between V.sub.SS and V.sub.IN. This voltage divider leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer become current bearing before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with CMOS fabrication techniques.

Abstract: A funnel-shaped monolithic low-density polyethylene sample-vial septum comprises a flange, a capture wall, a diffusion-barrier wall, and a membrane. The capture wall is conical, extending from its truncated apex at the diffusion barrier wall to its mouth about which the flange is disposed. The membrane is disposed at the end of the diffusion-barrier wall away from the capture wall. This structure defines a septum aperture, including a conical capture section, defined by the capture wall, and a cylindrical diffusion-barrier section, defined by the diffusion-barrier wall. The 7.0 mm length of the diffusion-barrier section is 12/mm times the square of its diameter 0.76 mm. The diameter of the diffusion-barrier section which is selected to be 0.05 mm greater than the diameter of the largest needle to be used with the septum, i.e., a 22 gauge needle typically used for liquid chromatography. The minimum thickness of the membrane is 0.

Abstract: A hybrid Harvard/Von Neumann data processing system utilizes a Harvard architecture processor with a combined data/instruction memory. A dual-port random-access instruction buffer between memory and the processor provides much of the performance enhancement of an instruction cache when used with a RISC instruction set, but at a much lower cost. The resulting system serves as an entry-level computer system of a series of compatible computers, led at the high end by a Harvard processor with full data and instruction caches.

Abstract: A method of forming a metal interconnect structure for a CMOS integrated circuit provides for deposition of via metal prior to formation of an intermetal dielectric. After a submetal dielectric is deposited, lower metal and via metals are deposited. Gradient photolithography is used to define a via pattern and a lower metal pattern in a positive photoresist. After etching, the lower metal assumes the lower metal pattern and the via metal assumes the via pattern. A three-layer intermetal dielectric includes a spin-on glass sandwiched between two deposited silicon dioxide layers. The resulting structure is polished until at least some of the vias are exposed. Other vias can be exposed by via apertures that are define photolithographically. An upper metal layer is then deposited, filling the via apertures. The upper metal is then patterned to complete the interconnect structure. This method provides that via metal is insulated from spin-on glass moisture by the deposited oxide.

Abstract: An electrically reconfigurable multi-chip module (MCERD) comprises three electrically reconfigurable integrated circuits (ERICs) enclosed in a package. The package provides for more "extra-package" connections between the ERICs and package pins than it does "intra-package" inter-chip connections. However, configuration connections between ERICs are intra-package. The MCERD is mounted on a daughterboard which provides connections between package pins and between package pins and pins of the daughterboard. The connections between package pins define "extra-package inter-chip" connections that typically far exceed the number of intra-package inter-chip connections. The connections between package pins and daughterboard pins connect the MCERD to a host system when the daughterboard is mounted on the host system motherboard. When the MCERD and daughterboard are installed in a host system, the MCERD can be electrically configured and then operated as configured.

Abstract: A branch circuit includes an branch breaker, a master outlet, and two slave outlets in series with the master outlet. The master outlet is the closest of the outlets to the circuit breaker. It includes a power sensor, the output of which is graphically displayed on a multi-segment LED display visible from the front of the outlet. The power sensor output is also supplied to displays at the slave outlets so that the power measured at master outlet is indicated at all outlets. This allows the available power capacity for the branch circuit to be appropriately indicated at all outlets on the circuit. The design can be implemented inexpensively enough that it is economical to employ the invention at every outlet in a building.

Abstract: A data-cascading hierarchically arranged electrically configurable logic device (ECD) system and an enable-cascading hierarchically arranged ECD system are provided. In both cases, the configuration bitstream includes a local count and at least one remainder count for each ECD. The local count determines the amount of configuration data to be stored locally. By setting this count to zero, an ECD can be bypassed. The remainder count determines the amount of data to be stored by devices down one hierarchical branch from the local ECD. By setting this count to zero, this branch can be bypassed and ECDs of a second branch can be configured sooner. In the data cascading system, the counts determine how data is routed through the ECDs. In the enable cascading system, the data is broadcast to all ECDs. The counts determine when and if the configuration enable inputs of downstream ECDs are to be activated.

Abstract: The present invention provides a bipolar transistor in which a lightly doped n-type hot-carrier shield extends in an epitaxial layer adjacent from a poly-emitter to an extrinsic base. This hot-carrier shield minimizes performance impairment that would otherwise occur due to a hot-carrier effect. Key steps in the method of making the bipolar transistor include a differential thermal oxidation while the poly-emitter is covered with a nitride cap. After the nitride cap is removed, an n-type dopant is implanted. The unprotected poly emitter is heavily doped. The implant partially penetrates a relatively thin oxide growth, thereby forming the hot-carrier shield. Other areas, such as the extrinsic base, and a polycrystalline base extension are covered by a relatively thick oxide growth and are unaffected by the n-type implant.

Abstract: A microprocessor provides for a single-cycle and a dual-cycle instruction mode. In the single-cycle mode, certain instructions, e.g., a "shift plus add" instruction, are performed in a single cycle with a relatively low clock rate. In the dual-cycle mode, the shift is performed in the first cycle and the add is performed in the second cycle with a relatively high clock rate. In the dual-cycle mode, a cycle can be dropped if the shift amount is zero or one of the operands is zero. A system designer and/or a programmer can select the mode to maximize throughput.