Abstract: An integrated circuit system includes an integrated circuit with a heat sink assembly including a fusible core. In the event that power dissipation by the integrated circuit threatens to exceed its safe operating range, the fusible core melts, absorbing the heat of fusion and delaying further temperature increases. A motor is repeatedly activated to attempt to rotate a shaft within the fusible core. When the core is solid, the shaft cannot be turned, but once it melts the shaft turns. The shafts motion is detected and used to trigger a reduction in the drive clock frequency of the integrated circuit. This reduces power consumption and dissipation until the integrated circuit cools and the heat sink core solidifies.

Abstract: The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. The pockets, like lightly doped drains, are formed after the gates are formed but before the formation of gate sidewalls. However, the input/output are masked during the punch-through implants, but are unmasked for at least one of the lightly doped drain implants. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.

Abstract: An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to generate a product). To this end, zero-prediction logic determines whether or not both of the following conditions are met: 1) either the least significant bits of the addends are the same and the carry-in is zero or the least significant bits of the addends are different and the carry-in is one. 2) for each pair of adjacent bit positions, the four included bits are consistent with addend complementarity. If both conditions are met, a zero result is predicted; otherwise, a non-zero result is predicted.

Abstract: A Harvard architecture data processing system includes a processor, main memory, an instruction cache, and a data cache. As is generally known with the Harvard architecture, these components are interconnected by an instruction bus, an instruction address bus, a data bus, and a data address bus. The instruction cache includes a branch target section and a general instruction section. For each instruction request by the processor, both sections are examined to determine if the requested instruction is in the cache. If it is, it is transmitted from the cache to the processor. If it is not, an instruction line including the requested instruction is fetched from main memory. If the requested instruction represents a jump (the result of an unconditional branch or a conditional branch the condition of which is met) the fetched instruction line can be stored only in the branch target section.

Abstract: A hermetically sealed microwave integrated circuit (MIC) includes a motherboard with a ground plane of aluminum-silicon alloy, a plastic/ceramic composite dielectric layer, and a copper-nickel-gold upper layer. The alloy for the ground plane is selected to allow fusion with aluminum containing less than 1% silicon to create a hermetic seal. The ground plane is fashioned to beyond the interior and upper layers, forming a welding flange that circumscribes the perimeters of the interior and upper layers. Recesses are cut into the dielectric to expose the ground plane. Active devices and microwave integrated circuits (MICs) are disposed within the recesses and mounted on the ground plane. The metallized upper layer is etched and patterned to create a microwave integrated circuit. The alloy flange is laser-welded to the annular lower surface of a frame made of aluminum containing less than 1% silicon, so that the interior plastic layer, the metallized upper layer, and all active devices are within the frame.

Abstract: A programming system for programming an electrically programmable gate array (EPGA) provides a clocked data signal with data cycles of the form 01DD, where the 01 ensures a clock transition each data cycle and the DD constitutes two bit periods with the same data value. The timing is led by a timing sequence of the form 0100. The EPGA measures the period of the timing sequence. For each data cycle, the EPGA detects the 01 transition, then, after a delay equal to twice the measured timing sequence period, generates a clock pulse. The series of clock pulses so generated constitutes a configuration clock. The configuration clock is used to time sampling of the clocked data signal to extract a configuration data signal. The configuration clock and the configuration data signal are used in a conventional manner to program configuration EPROMs of the EPGA.

Abstract: An AND array for an erasable programmable logic device (EPLD) includes word-line transition detectors for indicating high-to-low word-line transitions. Such transitions are a condition precedent for low to-high bit line transitions. Transition indications are buffered by a fast transition-detection sense amplifier, the output of which is provided to each of plural "mode-switchable" sense amplifiers that read out the bit lines for the AND array. Each mode-switchable sense amplifier logically combines the transition indication with its own output to select its operating mode. A fast (strong source-current) mode is entered only when,the transition indication is active and the present output of the sense amplifier is low. Otherwise, which is most of the time, the mode switchable sense amplifier remains in a low-power (weak source-current) mode. This arrangement provides higher speed operation with relatively low time-averaged power consumption.

Abstract: The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. The pockets, like lightly doped drains, are formed after the gates are formed but before the formation of gate sidewalls. However, the input/output are masked during the punch-through implants, but are unmasked for at least one of the lightly doped drain implants. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. Floating NMOS gates are capacitively coupled to V.sub.SS by a first-level metalization pattern. The metal-to-gate overlap capacitance and the gate-to-drain overlap capacitance define a voltage divider that leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer enter a conducting bipolar mode before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with gate array designs.

Abstract: A titanium-tungsten barrier layer is sputtered after active areas of a CMOS structure are exposed. An ion implant through the barrier layer and into the active areas disrupts the boundaries between the barrier layer and the underlying active areas. The implant can involve argon or, alternatively, silicon. The resulting structure is annealed. A conductor layer of an aluminum-copper alloy is deposited. An antireflection coating of TiW is deposited. The three-layer structure is then photolithographically patterned to define contacts and local interconnects. The ion implant before anneal results in less contact resistance, which is particularly critical for the barrier layer boundary with positively doped active areas.

Abstract: A floating-point processor comprises an input format converter, operand registers, a mode selector, an execution unit, and a result format converter. Inputs to the processor include first and second source values, low and high order result precision selectors, and an operation selector. The input format converter converts the source values to extended precision operands for storage in the registers. The mode selector is responsive to the apparent precisions, i.e., the numbers of trailing zeroes in the mantissas, of the operands as well as to the requested precision. The maximum of the requested result precision and the apparent precision determines the precision implemented by the execution unit. The results are stored in extended precision regardless of the execution precision. If the requested precision is less than extended, the result format converter converts the result to the requested format.

Abstract: An integrated circuit system includes an integrated circuit with a heat sink assembly including a fusible core. In the event that power dissipation by the integrated circuit threatens to exceed its safe operating range, the fusible core melts, absorbing the heat of fusion and delaying further temperature increases. A motor is repeatedly activated to attempt to rotate a shaft within the fusible core. When the core is solid, the shaft cannot be turned, but once it melts the shaft turns. The shafts motion is detected and used to trigger a reduction in the drive clock frequency of the integrated circuit. This reduces power consumption and dissipation until the integrated circuit cools and the heat sink core solidifies.

Abstract: A power conservation system (PCS) includes a data handler, a controller and a power switch. The data handler is located between a host network and a network printer, while the power switch is between an AC power source and the printer's power input. The PCS can thus shut down the printer during periods when no data is being sent to the printer. The PCS monitors data to and from the printer, allowing it to track the printer's state and to capture its network identification. State tracking permits the PCS to emulate the printer when it is down and when it is booting. Additionally, the information stored in a state memory of the data handler can permit the printer's last ready state to be reconstructed after it turns on and boots to a ready state. In some cases, the data handler can answer network requests without turning on the printer. Thus, the PCS provides for effective power conservation while remaining invisible to a user.

Abstract: In the fabrication of an integrated circuit, an intermetal dielectric is formed using a plural plasma processes that can be performed without having to transfer the wafer in the interim. This saves on wafer handling. A wafer with a patterned first metal wafer is placed into a plasma chamber. A relatively low-power noble gas plasma is applied to clean the wafer. A reactive plasma treatment is then used to deposit silicon dioxide to a thickness greater than ultimately desired. A noble gas plasma is used to etch back the silicon dioxide. Spin-on glass is then applied. The previous etch back aids the conformance of the spin-on glass to the underlying structure. The spin-on glass can be polished for further planarization. A second silicon dioxide layer can be deposited on top of the spin-on glass. Via apertures can be photolithographically defined through the three-layer dielectric. Finally, second layer metal is deposited and patterned.

Abstract: A silicon-on-insulator transistor structure includes a selectively thinned channel region, leaving the source and drain regions relatively thick. The relatively thin channel region provides for full depletion, larger current handling, and thus, faster operation. The relatively thick source and drain regions provide resistance to damage by electrostatic discharge. The transistor structure can be formed from a silicon-on-insulator wafer by performing a light, deep source/drain implant; a shallow, heavy source/drain implant is optionally performed at this stage. Source and drain regions are masked, while the channel regions are etched to the desired channel thickness. After the mask material is removed, a gate oxide can be grown; gates can then be defined. If it has not been performed earlier, the shallow heavy source/drain implant can be performed at this point. In addition, a channel threshold adjust implant can be performed after the channel regions are thinned and before the gates are formed.

Abstract: After gates are patterned in a submicron CMOS process, a halo implant is performed with sufficient energy that the halo implant penetrates the gate structures to below the transistor channel regions. Where the substrate is not masked by gate materal, the halo implant penetrates below drain and source regions. During diffusion, this halo limits lateral diffusion of the source/drain dopants. The resulting transistor exhibits enhanced breakdown voltage characteristics during both on and off conditions.

Abstract: A CMOS SRAM cell includes "true" and "false" NMOS word-line access transistors, "true" and "false" NMOS pull-down transistors, and "true" and "false" PMOS pull-down transistors arranged in a classical six-transistor SRAM electrical configuration. "True" and "false" inter-level interconnects of silicidable material provide for respective five-way connections among the transistors. The "true" inter-level interconnect connects: the drain of the "true" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "false" pull-up transistor and the "false" pull-down transistor, and a diffusion region defining and connecting the source of the "true" access transistor and the drain of the "true" pull-down transistor.

Abstract: The present invention provides a BiCMOS integrated circuit with bipolar, NMOS and PMOS transistors. In a bipolar transistor, an emitter buffer is provided to minimize a hot carrier effect. The emitter buffer is implanted using the same mask used for a base link. However, the n-type dopant is implant using a large angle, while the p-type dopant is implanted using a normal implant. A "base" oxide is grown over the implant region. This oxide ultimate isolates the emitter buffer from the polysilicon emitter contact section. Local interconnects are formed using a "dual-gate" technique, in which a tungsten silicide cap layer is formed over polysilicon to short pn junctions in the interconnect.

Abstract: Memory arrays of non-binary physical dimensions are disclosed. A novel addressing scheme provides that multiple word lines are activated in response to each received address code. Generally, at least two physical block rows containing blocks of an addressed logical block row are activated in response to each address. Block rows containing redundant blocks are activated in response to every address. In a specific embodiment, a 1 M-bit array arranged in 11 rows of blocks and 6 columns of blocks functions as an 8.times.8 block logical array, with two blocks available for redundancy. The availability of non-binary physical arrays affords a designer new flexibility in meeting packaging constraints and redundancy specifications.

Abstract: A photolithographic process involves the use of plasma to effect a superficial etch of a semiconductor wafer prior to the application of photoresist. Photoresist is applied directly on the wafer, without using an adhesion promotor. The photoresist is then exposed to patterned light. After exposure, the photoresist is developed leaving the desired photoresist mask on the wafer. Due to the superficial etch, curling of the photoresist is minimized, enhancing the selective protection provided by the photoresist to the wafer below.