Abstract: A semiconductor processing method provides for plasma-enhanced chemical-vapor deposition (PECVD) for intermetal dielectrics while minimizing risk of gate oxide impairment due to plasma discharge. A protective oxide sublayer is deposited without using high-power PECVD. The protective sublayer can be deposited by using chemical-vapor deposition (CVD) without plasma enhancement or by a lower-power PECVD. In the latter case, the initial rf power of the plasma is selected to be low enough to ensure that the gate oxide is not breached in the event of a plasma discharge. The protective sublayer can be thick enough to maintain its integrity in the event of a plasma discharge even during a higher-power PECVD deposition.

Abstract: A trip controller for a wafer processing system provides for adjustable hysteresis and autocalibration. Adjustable hysteresis implements different trip points for upward pressure changes and downward pressure changes in the wafer processing chamber. Autocalibration is implemented using a digital potentiometer with on-chip storage. The trip controller provides more reliable operation than conventional single trip-point indicators. Yet, the inventive trip controller is readily inserted as a replacement in systems formerly using conventional trip controllers. Further advantages include a single-rail power supply and flexibility to adapt to different systems requiring trip controllers.

Abstract: An event-driven logic simulator provides for future evaluation events. Evaluation latencies are assigned to respective inputs of components based on component type. At least some of these latencies are positive and finite. When a signal status event specifies a change at an input associated with a positive latency, the function for the component is not evaluated at the present time. Instead, the evaluation is postponed to a future time equal to the present time plus the assigned latency. The evaluation is thus latent until the scheduled time becomes present. When multiple evaluation events are indicated for a common component output, a queue manager resolves the conflicts by discarding all but one of the evaluation events for that output. This approach minimizes redundant and superfluous evaluations during circuit simulation.

Abstract: After a metal deposition is patterned using a plasma etch, the metal pattern is sprayed with steam and water. During the spraying the wafer is rotated to ensure proper distribution and removal of the spray. The spray removes chlorine residue from the etch that might otherwise corrode the metal pattern. After the spray, the spin rate is increased to dry the wafer. The net result is a faster and more effective method for chlorine removal from a plasma-etched metal pattern.

Abstract: Memory arrays of non-binary physical dimensions are disclosed. A novel addressing scheme provides that multiple word lines are activated in response to each received address code. Generally, at least two physical block rows containing blocks of an addressed logical block row are activated in response to each address. Block rows containing redundant blocks are activated in response to every address. In a specific embodiment, a 1 M-bit array arranged in 11 rows of blocks and 6 columns of blocks functions as an 8.times.8 block logical array, with two blocks available for redundancy. The availablity of non-binary physical arrays affords a designer new flexibility in meeting packaging constraints and redundancy specifications.

Abstract: An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.

Abstract: A static random access memory (SRAM) employs a modified divided word architecture in which each address selects cells from plural blocks. Thus, each word is dispersed among multiple blocks, rather than being confined to a single block as in conventional divided word architectures. More specifically, the blocks are divided among four quadrants of the array and data pads (or ports) are arranged on opposite sides of the array. This architecture causes each word to be divided among all four quadrants. Each quadrant is coupled via a respective data bus to the data ports adjacent to the quadrant. This arrangement reduces data path lengths within the SRAM, improving overall access times.

Abstract: Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.

Abstract: A circuit arrangement for monitoring two operating voltages of different polarity detects and indicates the deviation of either operating voltage from its nominal value beyond a predetermined tolerance limit. A transistor is provided, whose base is connected to the positive operating voltage across a first zener diode and to the negative operating voltage through a first resistor, and whose emitter is connected to the negative operating voltage through a series connection of a second zener diode and a second resistor, and to a reference potential across a diode.

Abstract: A receiver is configured as a multistage differential amplifier. A front differential transconductance amplifier provides complementary outputs which respectively control current sources for an intermediate differential amplifier and a final differential amplifier. The output of the intermediate differential amplifier controls the mirror-current load of the final differential amplifier. The final current source and the final mirror-current load are controlled so that they induce a push-pull effect on the current output. When a high output is required, the output current is increased to charge the output capacitance more quickly. When a low output is required, the augmented current source drains the output capacitance more quickly. The net result is an enhanced slew rate for the receiver. The receiver can thus operate at higher frequencies and handle greater information rates.

Abstract: Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.

Abstract: A static random access memory (SRAM) comprises plural memory cells, a true-bit load and a complementary-bit load, a true-bit line and a complementary bit line, a sense amplifier and an address transition detector. The address transition detector is used to generate load pulses which switch off the loads just after either of the memory cells is selected. This speeds signal development during a read (or write) operation. Since provision is made for modulating the loads, they can be designed to permit larger-than-conventional currents to flow therethrough when maximally on. The loads are maximally on just after cell deselection to facilitate bit-line equalization between cell selections. Thus, the present invention provides for briefer inter-select periods, quicker reads upon cell selection, and, thus, a faster SRAM overall.

Abstract: In a method for fabricating a MOS device, a nitride cap is formed over a remote interconnect of gate material. In a subsequent oxide growth step, oxide is formed over another remote interconnect and transistor gates, while the nitride cap prevents oxide growth over the first remote interconnect. Thinner oxide over source and drain regions is removed, leaving oxide formations over the gates and the second interconnect; the nitride cap is also removed. Silicide is then formed over the source and drain regions and over portions of the first remote interconnect. A conducting layer is deposited and a local interconnect is then patterned therefrom which electrically connects the first remote interconnect to at least one source/drain region without using via holes. This local interconnect crosses over the second remote interconnect, while being insulated from it by the oxide formation.

Abstract: A multi-stage output buffer provides for inactivation and then delayed reactivation of a second gain stage after a data transition. The delay imposed is a function of the output voltage, which is fed back through a threshold detector. A transition detector is coupled to data inputs so that it can inactivate the second gain stage upon a data transition; the transition detector is coupled to the threshold detector so that it can activate the second gain stage once the output voltage crosses a predetermined threshold voltage. This configuration imposes relatively long delays on second gain stage activation when large loads are applied to keep switching transients at tolerable levels. When lesser loads are applied, a shorter delay permits more rapid throughput.

Abstract: A quality control system provides for real-time, high-speed, high-resolution, comparison of the three-dimensional form of a sample with that of an examplar. The quality inspection system includes a sample analyzer, an exemplar analyzer, a comparator, a controller and a position memory. The sample analyzer includes a sample imager for providing an interferometric image of a sample of inspection, a sample scanner for scanning the sample image, and a sample transducer for converting the resulting sample scan into a sample signal representing the three-dimensional form of the sample. The exemplar analyzer similarly includes an exemplar imager, an exemplar scanner and an exemplar transducer to provide an exemplar signal representing an exemplary three-dimensional form for said sample. The comparator provides a comparison signal which identifies the scan times during which differences between the sample signal and the exemplar signal are detected.

Abstract: A septum for an injection port of a gas chromatograph includes interlocked syringe and duckbill seals. The syringe seal prevents fluid leakage during injection by syringe. The duckbill seal prevents fluid leakage after the syringe needle is withdrawn from the septum. A spring clip is used to urge the duckbill closed as the needle is withdrawn. An advantage of this two component septum is that the duckbill slit can be precisely formed in the duckbill seal before the seals are engaged.

Abstract: A high-power switch network includes a laser fiber optically coupled to a network including light-initiated glow discharge switches in a Marx configuration. A low pressure gas source is used to replenish gas within the switches lost due to ionization. Each switch has a cylindrical insulating envelope with conductive end caps at each end. The end caps are electrically coupled, respectively, to a cup-shaped anode and a cup-shaped cathode. Apertures are formed centrally in closely spaced plates of the respective cup-shaped electrodes. Optical fiber cables extend through vacuum sealed ports of the switches so that the unfocused laser light is directed about the aperture of the cathode so as to close the switch, thus providing a high power output from the network.

Abstract: An integrated circuit assembly (10) includes a bipolar VLSI die (12) contained in a multilayer ceramic pin-grid array package (14). A bonding shelf (18) defined on a single ceramic layer contains an inner row (20) of bonding pads (26) and an outer row (22) of bonding pads (28). Bonding wires (30, 32) extend from bonding pads (34) on the die to the opposing pads on the inner and outer rows to provide an electrical interface between the die and the package. The inner and outer bonding pads are connected by metallized fingers to conductive pads (61, 65) which provide a power and signal interface with an incorporating system.The inner pads include metallized vias (24) to metallized segments on a layer other than that on which the bonding shelf is defined. Thus, the metallized fingers including the inner row of pads can extend to the pins while passing above or below, rather than between, adjacent pads of the outer row.

Abstract: An integrated circuit package includes a case incorporating an integrated circuit die. The case has several ceramic layers, including layers with apertures for defining a die cavity and two layers without apertures which serve as thermal path layers. The thermal path layers include mutually staggered vias which conduct heat from the die cavity to a heat spreader separated from the die by the thermal path layers. The vias of the two layers are not electrically coupled so that the heat spreader is thermally coupled and electrically uncoupled with respect to the die. The thermal path layers, the thermal vias and other thermal path elements are fabricated from the same set of materials used in the cavity-defining layers, electrical vias and conductive strips.

Abstract: Normally, cyanoacrylates cannot be applied by brushing since they cure rapidly in contact with brush bristles. By pre-wetting the bristles with a solvent, this curing action is impeded. Thus, brushes so treated can be stored in a cyanoacrylate monomer formulation and the formulation can be brushed.This discovery permits cyanocrylates to be conveniently packaged in a bottle with cap and brush ready for use, for example, as fingernail strengthening and extenion systems. Thus, sophisticated fingernail enhancement systems can be distributed and used about as conveniently as fingernail polish systems.