Patents Represented by Attorney Cooley Godward Kronish LLP
  • Patent number: 7641815
    Abstract: Luminescent materials and the use of such materials in anti-counterfeiting, inventory, photovoltaic, and other applications are described herein. In one embodiment, a luminescent material has the formula: [AaBbXxX?x?X?x?][dopants], wherein A is selected from at least one of elements of Group IA; B is selected from at least one of elements of Group VA, elements of Group IB, elements of Group IIB, elements of Group IIIB, elements of Group IVB, and elements of Group VB; X, X?, and X? are independently selected from at least one of elements of Group VIIB; the dopants include electron acceptors and electron donors; a is in the range of 1 to 9; b is in the range of 1 to 5; and x, x?, and x? have a sum in the range of 1 to 9. The luminescent material exhibits photoluminescence having: (a) a quantum efficiency of at least 20 percent; (b) a spectral width no greater than 100 nm at Full Width at Half Maximum; and (c) a peak emission wavelength in the near infrared range.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: January 5, 2010
    Assignee: Ultradots, Inc.
    Inventors: John Varadarajan, Mirna Resan, Fanxin Wu, William M. Pfenninger, Nemanja Vockic, John Kenney
  • Patent number: 7642133
    Abstract: The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: January 5, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yen-Yi Wu, Wei-Yueh Sung, Pao-Huei Chang Chien, Chi-Chih Chu, Cheng-Yin Lee, Gwo-Liang Weng
  • Patent number: 7642048
    Abstract: The assays, methods, tools and systems discussed herein represent an improved and unified system for monitoring the progression of an individual patient malignancy. The assays, methods, tools and systems discussed herein represent an improved and unified system for monitoring and for identifying cellular and secreted markers, for screening cells to detect phenotypic and genotypic drift and for predicting chemotherapeutic response of patient tumor cells to at least one therapeutic agent. The assays, methods, tools and systems discussed herein also represent an improved and unified system for monitoring and for screening multiple pharmaceutical agents for efficacy and long term effect as to a specific patient.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: January 5, 2010
    Assignee: Precision Therapeutics Inc.
    Inventors: Michael Gabrin, Stacey Brower, Sean McDonald, Holly Gallion, Payal Nanavati, Shara Dawn Rice, Anuja Chattopadhyay
  • Patent number: 7644319
    Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: January 5, 2010
    Assignee: MIPS Technologies, Inc.
    Inventor: Radhika Thekkath
  • Patent number: 7638488
    Abstract: The present invention provides methods for treating a flavivirus infection, including hepatitis C virus (HCV) infection, in an individual suffering from a flavivirus infection. In some embodiments, the methods involve administering to an individual in need thereof an effective amount of an agent that inhibits enzymatic activity of a membrane-bound ?-glucosidase inhibitor. In other embodiments, the methods involve administering to an individual in need thereof effective amounts of an ?-glucosidase inhibitor and at least one additional therapeutic agent.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: December 29, 2009
    Assignee: Intermune, Inc.
    Inventors: Lawrence M. Blatt, Hua Tan, Scott Seiwert
  • Patent number: 7640427
    Abstract: This present invention provides users with secure transparent electronic communication, allowing them to send and receive encrypted and/or signed messages with little or no user involvement. In various embodiments, the present invention provides a user with e-mail security via automated hierarchical techniques for transparently sending and receiving secure messages, and lowers the burden on administrators. Such a system can also manage cryptographic keys and certificates for the users, and creates such keys and certificates for the users when necessary. A server according to the present invention can intercept unsecured messages from a user, automatically transform those messages into secured messages, and transmit those secure messages to the intended recipients. The server can also automatically transform messages after the recipient sends a digital identity to the server and downloads the software necessary for transforming the secured messages back into readable messages (i.e.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: December 29, 2009
    Assignee: PGP Corporation
    Inventors: Jonathan D. Callas, William F. Price, III, David E. Allen
  • Patent number: 7640261
    Abstract: A computer readable medium is configured to receive an identification of a plurality of data records, where each data record corresponds to one of a plurality of data record schemas represented in COBOL, and each data record schema corresponds to one of a plurality of standardized data record schemas. The computer readable medium is further configured to specify one of the plurality of standardized data record schemas as a selected standardized data record schema, and to process the plurality of data records based on the selected standardized data record schema.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: December 29, 2009
    Assignee: Business Objects Software Ltd.
    Inventors: Andrey Belyy, Alexander Ocher
  • Patent number: 7632521
    Abstract: A unit dosage form, such as a tablet for delivering potassium into the body in a controlled release fashion, comprises of a multiplicity of microencapsulated potassium chloride crystals, which are further coated with a plasticized polymer to improve compressibility of the microcapsules. The compressible microcapsules are blended with a compression aid, such as microcrystalline cellulose and a glidant, such as colloidal silicon dioxide, to form controlled release potassium chloride tablets. The tablets may optionally include other excipients such as surfactants and disintegrants. The tablets thus produced exhibit not only high crushing strength and low friability but also release potassium in humans in a desired controlled release fashion similar to commercially available potassium chloride tablets.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: December 15, 2009
    Assignee: Eurand, Inc.
    Inventors: Gopi Venkatesh, Craig Kramer
  • Patent number: 7633170
    Abstract: A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: December 15, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jun Young Yang, You Ock Joo, Dong Pil Jung
  • Patent number: 7633505
    Abstract: A multi-chip graphics system includes a master chip and a slave chip coupled by an interlink. The slave chip performs pixel processing in parallel with the master chip, improving the performance of the master chip. In one embodiment, an individual graphics processing unit (GPU) chip includes a normal operational mode, a master mode, and a slave mode to permit an individual GPU chip to be used as individual processor or to be utilized as part of a master/slave pair.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: December 15, 2009
    Assignee: NVIDIA Corporation
    Inventor: Brian M. Kelleher
  • Patent number: 7627794
    Abstract: An electronic circuit includes multiple computational cores. A test access protocol machine with a core address register and a signal routing control circuit addresses a selected computational core as specified by the core address register and routes output test data from the selected computational core.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: December 1, 2009
    Assignee: MIPS Technologies, Inc.
    Inventor: Ryan C. Kinter
  • Patent number: 7626420
    Abstract: An apparatus, system, and method are described for synchronously resetting logic circuits. A synchronous reset signal is coupled to at least one asynchronous reset input for synchronously resetting sequential logic. In one embodiment, reset logic generates a signal coupled to the at least one asynchronous reset input of the sequential logic to synchronously reset the sequential logic.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: December 1, 2009
    Assignee: NVIDIA Corporation
    Inventor: Elik E. Cohen
  • Patent number: 7627770
    Abstract: A processor comprises a processor core executing multiple threads. A bifurcated thread scheduler includes an internal processor core component and an external processor core component. The bifurcated thread scheduler identifies when all of the multiple threads are blocked and thereafter automatically enters a default low power sleep mode.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: December 1, 2009
    Assignee: MIPS Technologies, Inc.
    Inventor: Darren M. Jones
  • Patent number: 7627588
    Abstract: A computer implemented system and method automates analysis and mining of concepts from unstructured data. At least one concept within at least one object is analyzed. Analysis involves: selecting an object for inclusion in an initial set of objects to be analyzed; using an algorithm to extract a concept from the initial set of objects to create an initial set of concepts; refining the concept based upon relationships to other concepts; and performing multi-dimensional analysis on the concept in the initial set of objects to analyze the concept.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: December 1, 2009
    Assignee: Ixreveal, Inc.
    Inventors: Rengaswamy Mohan, Usha Mohan, David D. Sha
  • Patent number: 7617814
    Abstract: An apparatus includes a housing configured to receive a portion of a fuel pump. The housing defines a first flow path, a second flow path and a third flow path. The first flow path is in fluid communication with a fuel outlet portion of the fuel pump. The second flow path is in fluid communication with the first flow path. The third flow path is in fluid communication with the second flow path. A side wall of the housing defines a venturi within the second flow path at a location downstream from an intersection of the third flow path and the second flow path. A flow control member is disposed within the second flow path at a location upstream from the intersection of the third flow path and the second flow path. The flow control member is configured to regulate the fuel flow within the second flow path.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: November 17, 2009
    Assignee: Synerject, LLC
    Inventor: Kevin L. Leppert
  • Patent number: 7618362
    Abstract: An apparatus comprises an elongated delivery member and a scaffold. The elongated delivery member has a distal end, a fixed portion and an actuator portion. The actuator portion is disposed proximate to the distal end. The actuator portion and the fixed portion are movable with respect to each other. The scaffold is mounted to the elongated delivery member proximate to the distal end. The scaffold has a first end coupled to the fixed portion. The scaffold has a second end coupled to the actuator portion. The scaffold is changeable between a stowed configuration and a deployed configuration by movement of at least the actuator portion and the fixed portion relative to each other.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: November 17, 2009
    Assignee: Boston Scientific Scimed, Inc.
    Inventors: Paul DiCarlo, Robert F. Rioux
  • Patent number: 7620913
    Abstract: A node-link structure is displayed within a display area having a narrow rectangular shape with an edge along one side acting as a horizon of a hyperbolic space half-plane. Lower level node features that share a parent node feature have centers of area positioned on the display in order along a line parallel with the horizon, with sufficiently similar spacings along an axis perpendicular to the horizon from the region around a parent node feature, and with sufficiently similar spacings in a dimension parallel to the horizon from adjacent node features along the line, that the lower level node features sharing the parent node feature are perceptible as a group of related node features. The half-plane model with compression is used for layout of the node-link data, and the hyperbolic layout data is mapped to a Euclidean space for display.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: November 17, 2009
    Assignee: Business Objects Americas
    Inventors: Yozo Hida, John O. Lamping, Ramana B. Rao
  • Patent number: 7620764
    Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: November 17, 2009
    Assignee: Stretch, Inc.
    Inventor: Charle′ R. Rupp
  • Patent number: 7617348
    Abstract: A bus interface controller manages a set of serial data lanes. The bus interface controller supports operating a subset of the serial data lanes as a private bus.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: November 10, 2009
    Assignee: NVIDIA Corporation
    Inventor: Radoslav Danilak
  • Patent number: D604379
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: November 17, 2009
    Assignee: Swimways Corporation
    Inventor: James Harmon