Patents Represented by Attorney, Agent or Law Firm Coudert Brothers
  • Patent number: 6454727
    Abstract: A tissue acquisition system includes radio frequency (RF) cutter loops which are extendable out a cannula to cut cylindrical tissue samples from a tissue of interest in a patient. The cannula includes inner and outer cannulae which are mutually rotatable and include cutouts through which the cutting loop can be rotated and longitudinally extended to perform the cuts. The tissue samples are then aspirated proximally through the cannula for collection.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: September 24, 2002
    Assignee: SenoRx, Inc.
    Inventors: Fred Burbank, Paul Lubock, Michael L. Jones, Martin V. Shabaz
  • Patent number: 6456233
    Abstract: The measurements of two GPS and/or GLONASS receivers are related to a common time moment by extrapolating measurement data that has arrived through a connection link with a delay. This common time moment is defined by the user. Cycle slips in the phase-lock loops (PLLs) of the receivers, which may be caused by blockage of direct signals from the satellites, strong interference signals, and reflections, are deflected and corrected in a multi-loop nonlinear tracking system. The procedure of resolution of phase measurement ambiguities comprises the preliminary estimation of floating ambiguities by a recurrent (e.g., iterative) procedure including the simultaneous processing of code and phase measurements for all satellites for each processing time interval, and the gradual improvement of the result as the information is accumulated. After the resolution of ambiguity, the user coordinates are estimated with centimeter accuracy on the basis of phase measurements on the carrier frequency.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: September 24, 2002
    Assignee: Topcon GPS LLC
    Inventors: Mark Isaakovich Zhodzishky, Victor Abramovich Veitsel, Michail Y. Vorobiev, Javad Ashjaee
  • Patent number: 6454604
    Abstract: An enclosure for small power supplies for cellular telephones, laptop computers and the like is formed in two layers. The first layer is an inner box constructed of a pair of about 0.8 mm thick PBT shells that enclose and retain the electronics. The second layer is an overmolding of about 1.0 mm. thick PVC that surrounds the shells, seals them together, and forms a strain relief for a cable attached to the electronics. The two-layer construction allows considerable savings in material and assembly costs.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: September 24, 2002
    Assignee: Astec International Limited
    Inventors: Gordon Currie, Fidel Vista, Peter Ramos Yeo, Cesar Calma, Anthony Hernandez
  • Patent number: 6454362
    Abstract: A cooling device for a portable electronic comprises a radiation plate and a fin for radiating the heat from the CPU. When the plug of an external power. supply is attached to the body of the portable electronic, the CPU may operate at a high clock frequency. The cooling device achieves a high cooling performance by operating a ventilation fan directed to the fin, for example. When the plug is removed from the body of the portable electronic, the CPU may operate at a low clock frequency. Power consumption can be reduced, so that the electric power stored in the built-in battery can be saved. The duration time of the operation can be extended. Calorific power generated at the CPU can also be reduced, so that the cooling device is adapted to suppress the rise in the temperature of the CPU without operation of the ventilation fan.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: September 24, 2002
    Assignee: Fujitsu Limited
    Inventors: Tadashi Katsui, Keizo Takemura, Minoru Hirano, Masumi Suzuki, Yoshiaki Udagawa, Masuo Ohnishi, Kenichi Fujii
  • Patent number: 6448852
    Abstract: A compact polarity-insensitive integrated circuit amplifier is described designed to be powered by a miniature low voltage battery of variable polarity. Low current, polarity corrected voltage sources are integrated into functional blocks to supply low current non-bidirectional elements and to provide a constant polarity bias to a substrate of CMOS circuits. Polarity corrected voltage sources are used to provide a polarity sensing function. The invention is embodied in a Class D amplifier which may comprise four n-channel MOSFET transistors arranged in an H-bridge configuration. Additional driver circuitry is described which increases the voltage of the pulse-width modulated input signal to the MOSFET transistors and also performs a pulse trimming function, which reduces parasitic crowbar currents in the amplifier output stage.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: September 10, 2002
    Assignee: The Engineering Consortium, Inc.
    Inventors: James Barclay Compton, Clyde “Kip” M. Brown, Jr.
  • Patent number: 6448759
    Abstract: A non-contact linear position center has juxtaposed transmit and receive sections with a coupler or slider section interposed therebetween carrying a symmetrical attenuating conductive pattern. The inductive coupling of coils on the transmitter and receive sections is attenuated in accordance with the linear position of the pattern on the coupler. A unique sinusoidal signal is generated whose phase is indicative of the linear position of the coupler.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: September 10, 2002
    Assignee: BEI Sensors and Systems Company, Inc.
    Inventors: Asad M. Madni, Jim B. Vuong
  • Patent number: 6449410
    Abstract: An integrated two-dimensional tunable filter array for a matrix of fiber-optic input-output light channels includes a tunable filter chip array sandwiched between a first semiconductive wafer in which the guiding grooves for the input light channels terminate in a 45° reflecting surface causing a 90° turn of the light beams into each tunable filter of the array. Then a third semiconductive substrate is bonded to the other side of the tunable filter array to receive the reflected light beams. A 45° mirror on a {111} plane may be formed by slow etching of a {100} type wafer or the use of a {100} type wafer with a 9.7° off axis cut.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 10, 2002
    Assignee: Optic Net, Inc.
    Inventor: Long Que
  • Patent number: 6449175
    Abstract: A switched magamp post regulator in a power converter incorporating a switched set mode control circuit which minimizes the power loss associated with the control transistor of a set mode magamp post regulator is disclosed. Power loss in set mode is minimized by switching the control transistor on and off synchronously with the main transformer. The incorporation of set mode and switching allows the use of less expensive ferrite core materials with increased efficiency for operation at higher frequencies and higher temperatures.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: September 10, 2002
    Assignee: Astec International Limited
    Inventors: Jason Cuadra, Manolo Mariano M. Melgarejo
  • Patent number: 6448106
    Abstract: Device modules with pins and methods for making device modules with pins are disclosed. One embodiment is directed to a method including forming a polymeric circuit structure having a first side and a second side on a substrate. The formed first side is adjacent to the substrate. A pin is bonded to the second side of the polymeric circuit structure. At least a portion of the substrate is removed to expose at least a portion of the first side of the polymeric circuit structure, and a device is mounted on the first side of the polymeric circuit structure.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: September 10, 2002
    Assignee: Fujitsu Limited
    Inventors: Wen-chou Vincent Wang, Thomas J. Massingill, Yasuhito Takahashi, Lei Zhang
  • Patent number: 6445233
    Abstract: A rectifier circuit produces an output which is a function of the magnitude of an input signal and has a controllable transient response. The circuit requires no rectification diodes. The voltage on a capacitor is sensed and compared with that of an input voltage. The operation of charging and discharging switches is adjusted by a control circuit to charge the capacitor if the magnitude of the input signal is greater than the capacitor voltage and to discharge the capacitor if the magnitude of the input signal is less than the capacitor voltage. The attack and release function of the rectifier is selectable by limiting the rate at which current charges/discharges the capacitor, preferably with constant current sources comprised of current mirrors. Multiple time constants are achieved by replicating the storage capacitor and charge/discharge elements configured with different time constants and then summing the resultant capacitor voltages.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: September 3, 2002
    Assignee: The Engineering Consortium, Inc.
    Inventors: Hoang Minh Pinai, Clyde “Kip” M. Brown, Anthony J. Becker
  • Patent number: 6444921
    Abstract: Disclosed is an interposer for electrically coupling two electrical components having different coefficients of thermal expansion (CTEs). The interposer has two substrates which have different CTE values, with each substrate having a first surface and a second surface. The interposer has electrical connectors located on the first surfaces of the two substrates, the connectors for making electrical connections to the two corresponding electrical components. A flexible-circuit layer is disposed between the two substrates and interconnects the connectors on the first substrate to the connectors on the second substrate. The two substrates are folded such that their second surfaces confront one another, where they may be attached to one another. General methods of making interposers for electrically coupling two electrical components are disclosed.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: September 3, 2002
    Assignee: Fujitsu Limited
    Inventors: Wen-chou Vincent Wang, Michael G. Lee, Solomon Beilin
  • Patent number: 6445571
    Abstract: A combination DC/data bus assembly for power converter equipment racks includes a pair of side-by-side vertical DC bus bars forming a slot between them. Extruded insulating strips carrying data bus bars are mounted in the DC bus bars so that the data bus bars face each other across the slot. Channels are formed in the front faces of the DC bus bars. A connector mounted on the power converter chassis has male DC contacts that engage the channels, and a male data contact assembly that slides into the slot to make contact with the data bus bars.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: September 3, 2002
    Assignee: Astec International Limited
    Inventors: Brian Inniss, Michael Hutchins
  • Patent number: 6442749
    Abstract: A software architecture for task oriented applications. The architecture utilizes a wrapper as an intermediate structure between an external calling application and a wrapped component or module. The wrapper is written in a script language and acts as a bridge between the external application and the wrapped component. Data is transferred among components through the intermediary of a table of contents (TOC) file which contains data attribute information and a link to the actual data file.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: August 27, 2002
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Hirao, Hirokatsu Araki, Tadashi Takahashi, Hitoshi Matsumoto, Masaru Wakitani
  • Patent number: 6442589
    Abstract: An electronic message forwarding system selectively forwards information to a plurality of different receiving device types. One or more user defined filters filter incoming messages, route the messages, and send the routed message to appropriate form converters to convert the message into a form appropriate to the receiving device type, such as e-mail, pager, facsimile, or telephone forwarding. In a preferred embodiment, a plurality of filters, router, and form converters may be used to perform a message classification, channel selection, and channel output control function.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: August 27, 2002
    Assignee: Fujitsu Limited
    Inventors: Tadashi Takahashi, Takeshi Kumazawa, Hirokatsu Araki, Tsuyoshi Hirao, Hitoshi Matsumoto
  • Patent number: 6434029
    Abstract: A boost converter topology is disclosed that includes a resonant network comprising a snubber inductive element having a primary winding connected in series to a first resonant diode that is connected, at a first node, to two series connected additional resonant diodes and a secondary winding coupled to a fourth resonant diode connected to the first node. The present invention has the advantage of reducing the energy stored in the parasitic capacitor of the first resonant diode by a factor of four at the turn off of the main control switch. This reduction is achieved by allowing only a small amount of energy transfer to the snubber inductive element so that it does not turn the two additional resonant diodes on before the auxiliary switch is turned on, thus reducing losses and EMI associated with turning on the auxiliary switch.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: August 13, 2002
    Assignee: Astec International Limited
    Inventors: Jean-Marc Cyr, Richard Verreau
  • Patent number: 6428942
    Abstract: Methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: August 6, 2002
    Assignee: Fujitsu Limited
    Inventors: Hunt Hang Jiang, Yasuhito Takahashi, Michael Guang-Tzong Lee, Wen-chou Vincent Wang, Mark McCormack
  • Patent number: 6429882
    Abstract: A user interface component. One or more embodiments provide a framework to develop a graphical user interface (GUI) for applications and to present information to a user. The framework provides a common look, feel, and usage with a layout that may follow a designated style guide. Aspects of a business (e.g., customers, vendors, or invoices) are created in the form of business objects. An editor that provides the ability to display and modify attributes of each business object (e.g., the address, name and phone number may be attributes of a customer object) is created. A set of commands that implement the changes made in an editor and that are executed upon execution of an event (such as the selection of a button on a display, e.g., a “save” button) are also defined. One or more embodiments of the invention provide for the defining of information relating to a GUI's menu bar, tool bar, and action bar. Such user interface information may be provided in a properties file.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: August 6, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Alejandro H. Abdelnur, Chris Ferris
  • Patent number: 6427081
    Abstract: Detectable markers that may be introduced into a cavity created by removal of a biopsy specimen to mark the location of the biopsy site so that it may be located in a subsequent medical/surgical procedure. The markers remain present in sufficient quantity to permit detection and location of the biopsy site at a first time point (e.g., 2 weeks) after introduction but clear from the biopsy site or otherwise not interfere with imaging of tissues adjacent the biopsy site at a second time point (e.g., 5-7 months) after introduction.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: July 30, 2002
    Assignee: SenoRx, Inc.
    Inventors: Fred H. Burbank, Paul Lubock, Michael L. Jones, Nancy Forcier
  • Patent number: 6424208
    Abstract: An integrated transient voltage pulse multiplier is used to increase the voltage to the gates of control switches in a low voltage circuit. The increased conductance of the control switches permits a reduction in gate width, reducing parasitic charge injection and capacitive feedthrough. A low distortion switched capacitor filter utilizes two transient voltage pulse multipliers to increase the voltage of non-overlapping clock signals. The switched capacitor filter is operative at a power supply voltage of less than 1.5 volts.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: July 23, 2002
    Assignee: The Engineering Consortium, Inc.
    Inventor: Hoang Minh Pinai
  • Patent number: D463104
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: September 24, 2002
    Inventor: Timothy R. Ames