Patents Represented by Attorney, Agent or Law Firm D'Alessandro & Ritchie
  • Patent number: 6327309
    Abstract: A bidirectional communications interface employs the same path for transmitting and receiving. The bidirectional communications interface includes one two winding transformer for both transmit and receive and an integrated circuit having a transmitter and a receiver each connected to the same pair of input/output pins. The interface enables a communications node in a communications network to transmit data to and receive data from other nodes in the network.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: December 4, 2001
    Assignee: LSI Logic Corporation
    Inventors: Stephen F. Dreyer, Lee-Chung Yiu, Robert X. Jin
  • Patent number: 6215325
    Abstract: A ripple-data function unit having a ripple function and a data function for use in a priority circuit is described. The ripple-data function unit may be used to implement a priority encoder or a priority to 1-HOT recoder simply by defining the ripple and data functions as Boolean functions representing the ripple and arithmetic characteristics of the priority circuit desired. For example, at least one instance of a ripple-data function unit may be used to define a priority encoder if each instance includes ripple and data functions equivalent to the ripple and arithmetic characteristics of the priority encoder. Similarly, at least one instance of ripple-data function unit may be used to define a priority to-1-HOT recoder if each instance includes ripple and data functions equivalent to the ripple and arithmetic characteristics of the priority to 1-HOT recoder.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: April 10, 2001
    Assignee: Synopsys, Inc.
    Inventor: Jay Roger Southard
  • Patent number: 6212561
    Abstract: The present invention is a method and apparatus for providing the owners of domain sites on a computer network or the owners of private remotely accessible intra networks the capability to force authorized users to disconnect from any open connections to other public or private domains or networks before a connection with the owners domain or network can be established. This forced sequential access of a specified domain or network is accomplished by inserting a sequential-only attribute into the service profile for a specified user. Upon the user initiating a log-on sequence through an access point, the user's service profile is pulled from a memory bank and an assessment is made as to whether or not the sequential-only attribute exists for the desired specified domain or network to be accessed.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: April 3, 2001
    Assignee: Cisco Technology, Inc.
    Inventors: Aravind Sitaraman, Shuxian Lou, Shujin Zhang
  • Patent number: 6201875
    Abstract: A method for fitting a hearing compensation device comprises selecting a plurality of loudness levels for a plurality of frequencies and comparing each loudness level for each frequency for perceived sameness. The loudness levels may then be adjusted as needed to achieve perceived sameness across the frequency spectrum. A gain curve for each frequency is calculated from the selected plurality of loudness levels.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: March 13, 2001
    Assignee: Sonic Innovations, Inc.
    Inventors: Keith L. Davis, Xiaoling Fang, Darrell Rose, Douglas M. Chabries
  • Patent number: 6188975
    Abstract: The present invention is a method that uses breakpoints in a debugging program to signify to a hardware software co-verification tool when to redirect hardware calls to a hardware simulator. The method includes executing a line of software code within a software component, determining whether the line of software code requires interaction with a hardware device, associating the line of software code with an interface module if the line of software code requires interaction with a hardware device, simulating the hardware device with a hardware model running under simulation, using the interface module to request a hardware operation from the hardware model when the line of software code requires a hardware operation; and providing data generated by the hardware model running under simulation in response to the request.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: February 13, 2001
    Assignee: Synopsys, Inc.
    Inventor: Donald L. Gay
  • Patent number: 6185550
    Abstract: A method for classifying a document based on content within a class hierarchy. The class hierarchy comprises a plurality of category nodes stored within a tree data structure. Each of the plurality of category nodes includes a category name corresponding to a unique directory and a category definition comprising a set of defining terms. The class hierarchy is searched to determine appropriate categories for classification of the document. The document is then stored in directories corresponding to the categories selected for classification. If no categories are produced by the search, a system administrator is notified of the unsuccessful search.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: February 6, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: William A. Snow, Joseph D. Mocker
  • Patent number: 6181203
    Abstract: A nonlinear transconductance provides a nonlinear output in response to a differential signal input. In a switch-type closed loop system, such as switching mode DC—DC converter of phase lock loop, the nonlinear transconductance amplifier provides a very fast response time. The nonlinear transconductance amplifier is a linear transconductance amplifier that has been modified to include a nonlinear output stage of current mirrors having resistive elements connected to the emitters of the diode connected transistors in the current mirrors.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: January 30, 2001
    Assignee: Semtech Corporation
    Inventor: Trevor M. Newlin
  • Patent number: 6179938
    Abstract: A method of aligning the bonding head of a bonder, in particular a die bonder, or of a pick and place machine comprising the steps of a) placing an alignment plate provided with two plane parallel surfaces on a supporting surface which is set plane parallel to the bonding surface upon which the semiconductor chip will be bonded to the carrier material; b) calibration of a measuring device, the signal of which is dependent upon the position of the alignment plate; c) grasping the alignment plate with the bonding head of the bonder and holding the alignment plate free at a slight distance above the measuring device; and d) alignment of the bonding head until the signal from the measuring device is equal to the signal following step b).
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: January 30, 2001
    Assignee: Esec SA
    Inventors: Eugen Mannhart, Alois Ulrich, Thomas Guenther, Matthias Krieger
  • Patent number: 6178429
    Abstract: A mechanism for guaranteeing a coherent repository, including a list of requested files that are to be committed to the repository or to be processed (e.g. read) by an operation, and a list of “protected” files that are currently being processed. Either all of or none of the requested files are committed or are processed. Therefore, if any one of the requested files is in the protected-files list, then the invention waits until none of the requested files is protected before committing the requested files to the repository or before processing the requested files. An abnormal operation may hold up the protected files in the protected-files list for an unreasonably-long period of time. The invention thus provides an alarm mechanism, which scans the protected-files list to detect whether an abnormal operation exists. If such an operation is found, then the invention alerts an alarm agent and replaces the inconsistent files caused by the abnormal operation.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: January 23, 2001
    Assignee: Cisco Technology, Inc.
    Inventor: Scott Cherf
  • Patent number: 6172538
    Abstract: A method and an apparatus for reading a given digital pulse signal of variable length in the domain of a first clock frequency and creating a pulse output signal that is synchronized in the domain of a second clock. The number of cycles the input pulse signal is active, in terms of the first clock, is the same number of cycles as the resulting output signal is active, where for the output signal the number of cycles is measured by the second clock.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: January 9, 2001
    Assignee: Chips & Technologies, L.L.C.
    Inventor: Pierre M. Selwan
  • Patent number: 6163287
    Abstract: A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the plurality of transconductance amplifiers is coupled to the input of the integrator, a switched capacitor low pass chain having an input and a plurality of branches wherein each of the plurality of branches is coupled to the input of a separate one of said plurality of transconductance amplifiers, and a feedthrough branch having an input and an output wherein the input is coupled to the input of the switched capacitor low pass chain to form an input of said hybrid loop filter, and the output is coupled to the input of a separate one of the plurality of transconductance amplifiers.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: December 19, 2000
    Assignee: Sonic Innovations, Inc.
    Inventor: Renyuan Huang
  • Patent number: 6157870
    Abstract: Supply of tape components in which a tape replacement can be performed without any loss in performance is provided for by unwinding a first tape from a first reel, moving components located in the pockets of said first tape to a pickup position where they are picked up by a placement machine, splicing the end of said first tape to the start of a second tape wound on a second reel, and replacing said first reel by said second reel. A splice sensor is included for detecting a splice between the first and second tape. The signals from such splice sensor allow for an automatic and synchronous take over of the related data of the newly joined second tape.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: December 5, 2000
    Assignee: Zevatech Trading AG
    Inventors: Martin Gfeller, Otto Christen, Emil Grunder
  • Patent number: 6157683
    Abstract: A method and system for compensating for code invariancies in a digital communication receiver is performed on demodulated signal data. A pre-Viterbi invariancy compensation is performed on the demodulated signal data to reverse a selected one of a number of possible transformations to create compensated signal data. The compensated signal data is then depunctured. The depunctured data is then decoded. An encoder encodes the decoded data. The encoded data and the depunctured data are then compared to determine equivalence. The pre-Viterbi invariancy compensation is performed to reverse a different one of the number of possible transformations to create the compensated signal data when the encoded data and the depunctured data are determined not to be equivalent. A post-Viterbi invariancy compensation is then performed on the decoded data to produce a set of compensated outputs. Thus, the post-Viterbi invariancy compensation reverses each one of the number of possible transformations on the decoded data.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: December 5, 2000
    Assignee: LSI Logic Corporatino
    Inventors: Dariush Daribi, Advait Mogre, Daniel Luthi
  • Patent number: 6157250
    Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: December 5, 2000
    Assignee: Cisco Technology, Inc.
    Inventor: Sergio D. Camerlo
  • Patent number: 6157251
    Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: December 5, 2000
    Assignee: Cisco Technology, Inc.
    Inventor: Sergio D. Camerlo
  • Patent number: 6157952
    Abstract: An access control device controller and method of operation are provided which provide in a first aspect of the invention, a novel way in which to set controller network addresses providing a visually perceivable digital readout to assist installers in setting the correct address, in a second aspect of the invention, automatic configuration of end of line termination resistors, line biasing resistors and earth ground connection to the network medium shield, in a third aspect of the invention, automatic configuration of a controller/host computer data communications link, in a fourth aspect of the invention, a novel method and apparatus for monitoring ambient RF noise levels, and in a fifth aspect of the invention, a novel method of detecting environmental conditions likely to lead to a system failure.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: December 5, 2000
    Assignee: Keri Systems, Inc.
    Inventors: Kenneth J. Geiszler, Mark W. Lee, Robert D. Kohler
  • Patent number: 6154371
    Abstract: A printed circuit board assembly incorporates an opening into which one or more integrated circuit packages at least partially fit, a plurality of electrical connection pads are disposed about the periphery of the opening, corresponding leads of the integrated circuit package are bonded to the pads, and the overall assembly is thinner than an assembly lacking the opening.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: November 28, 2000
    Assignee: Cisco Technology, Inc.
    Inventors: Glenn George Oba, Indrajit Rajeev Gajendran, Victor Vigdorchik
  • Patent number: 6144565
    Abstract: A switched mode DC-DC power converter of the flyback type includes a primary circuit and a secondary circuit capacitively coupled to one another. In a first aspect the primary includes circuitry for achieving a 2:1 current transfer gain over the input, in a second aspect the secondary includes circuitry for achieving a 2:1 current transfer gain over an input. Combined, a 4:1 current transfer gain may be realized.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: November 7, 2000
    Assignee: Semtech Corporation
    Inventor: Patrice R. Lethellier
  • Patent number: 6144581
    Abstract: A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: November 7, 2000
    Assignee: California Institute of Technology
    Inventors: Christopher J. Diorio, Carver A. Mead
  • Patent number: RE37069
    Abstract: The present invention relates to An apparatus for converting cathode ray tube (CRT) data to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame four panel refresh frames. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: February 27, 2001
    Assignee: Chips & Technologies, LLC
    Inventors: Ignatius B. Tjandrasuwita, James E. Margeson, III