Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Abstract: A load emulator provides a high current load having a specified high slew rate to replicate the load and transient currents generated by advanced high speed microprocessors. The load emulator is implemented in the form of an L-C delay line having taps between separate load stages wherein each of the load stages provides a load which forms a portion of the total load in the load emulator. The load emulator, can achieve and exceed a current slew rate of 1 ampere per nanosecond, and can achieve and exceed a load current of 50 amperes.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A hearing compensation system comprises an input transducer for converting acoustical information at an input thereof to electrical signals at an output thereof, a differential analog-to-digital converter sampling the electrical signals output from the input transducer at an input thereof and outputting differential signal samples at an output thereof, a digital signal processing circuit having an input connected to the output of the differential analog-to-digital converter and operating on the differential signal samples to form processed differential signal samples at an output thereof, and an output transducer for converting electrical signals at an input thereof to acoustical information at an output thereof, the processed differential signal samples coupled to the input of the output transducer.

Abstract: A computer system is programmed to display a set of order triplet icons which are linked together to represent a medical treatment plan. Each of the order triplet icons represent a step within the medical treatment plan. Each link between two order triplet icons, such as a first order triplet icon and a second order triplet icon, represents a sequence between two steps within the medical treatment plan. Each sequence, as represented by a link, includes a rule which may be configured to have a time delay. When configured to have a time delay, the second order triplet icon is activated upon expiration of the time delay, forming a sequence from the first order triplet icon to the second order triplet icon. The computer system may also be programmed to display a medical treatment plan in process flow form, referred to as a publisher's view.

Abstract: A door stop having a retaining member having a shell defining a cavity, and a ledge extending outwardly from a lower portion of the shell, and an elastomeric bumper received in the shell cavity and having an exposed front surface, with the ratio of the length of the exposed bumper front surface to the thickness of the ledge is greater than about 8.0.

Abstract: A method for displaying grey-scale images at a desired grey scale resolution on a display having a matrix of pixels, comprises the steps of: defining a control matrix having a size smaller than the entire display and equal to the desired grey scale resolution of the display, each position in the control matrix having an address assigned such that unintended artifacts in the display are controlled; horizontally and vertically mapping the control matrix into the display such that each pixel in the matrix of pixels in the display corresponds to an address in a control matrix mapped into the display; comparing control matrix address of each pixel in a frame of an image to be displayed on the display to a range of address values and turning that pixel on if the grey scale value of that pixel is within the range of address values, the range of address values arranged in a circular queue and being equal to the grey scale value of that pixel; and shifting the range of address values in the circular queue for successi

Abstract: A method and apparatus for dithering for color computer display systems includes the addition of a noise component to each of the color components of each pixel in a pseudo-random manner. The noise component is preferably different for each color component. Taking the image as a whole, the noise component repeats on a regular basis but is preferably selected so as not to repeat on adjacent pixels. The image is divided into squares of pixels and the same noise component is added to each of the same relative pixels from square to square. The preferred square of pixels is four pixels wide by four pixels high. The value of the noise component is chosen such that the most significant bit alternates both horizontally and vertically from pixel to pixel within the square of pixels.

Abstract: The present invention provides for the accurate placement of an object having a surface pattern by relating the perimeter of the object to the surface pattern, such as a circuit pattern of a semiconductor die. This includes illuminating the object at its front and rear faces and viewing the object with a machine vision system. Front-side illumination of the surface pattern enables the machine vision system to obtain an image of the actual position of the circuit pattern or other pattern of interest on the front of the component. Rear illumination provides a silhouette of the perimeter edges of the component enabling the machine vision system to obtain the actual position of the perimeter edges of the component. A corrective offset from a normative feature location, such as the centroid defined by the perimeter edges of the component, is then calculated.

Abstract: Methods for recognizing gestures made by a conductive object on a touch-sensor pad and for cursor motion are disclosed. Tapping, drags, pushes, extended drags and variable drags gestures are recognized by analyzing the position, pressure, and movement of the conductive object on the sensor pad during the time of a suspected gesture, and signals are sent to a host indicating the occurrence of these gestures. Signals indicating the position of a conductive object and distinguishing between the peripheral portion and an inner portion of the touch-sensor pad are also sent to the host.

Abstract: A method for incremental recognition of ideographic handwriting comprises in order the steps of: (1) entering in a natural stroke order at least one stroke of an ideographic character from a computer entry tablet; (2) providing the at least one stroke to an incremental character recognizer, which produces a hypothesis list of at least one candidate character; (3) displaying a hypothesis list of candidate characters containing the at least one stroke; (4) selecting a correct character from among the candidate characters on the hypothesis list if it a correct character appears thereon; (5) entering in natural stroke order at least one additional stroke of the ideographic character from the computer entry tablet if no candidate character is a correct character; (6) providing the additional stroke(s) to the incremental character recognizer, which produces an updated hypothesis list; (7) displaying the updated hypothesis list of candidate characters containing every stroke; (8) selecting a correct character from a

Abstract: An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array.

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.OE17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 .mu.m. The thickness of the third (p+) region should be between about 0.3 .mu.m and about 2.0 .mu.m, and the thickness of the second (p-) region should be between about 0.5 .mu.m and about 5.0 .

Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting from a first signal a first plurality of bits of signal information to be processed, selecting from a second signal a second plurality of bits of signal information to be processed, reading the first plurality of bits of signal information into contiguous memory space so as to form a first word, reading the second plurality of bits of signal information into contiguous memory space so as to form a second word, causing a first logical AND operation to be performed on the second word with a mask, causing a first logical OR operation between the first word and the complement of the mask, causing a first EXCLUSIVE OR operation between the first word and the complement of the second word, causing a second logical AND operation between the results of the first EXCLUSIVE OR operation and the complement of the mask, subtracting the results of the first logical AND operati

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A method and apparatus for inserting an event into a simulation time queue, wherein the simulation time queue is represented by a tree structure having a top node which represents the total number of "time slices" to be simulated, intermediate nodes representing subsets of time slices within the total number of time slices to be simulated, and event locations representing events to be simulated. A time slice is defined to represent a minimum resolvable time period within the simulation. The method includes the steps of choosing a starting node within the tree structure, designating it as the current location, determining whether the current location is an intermediate node representing a range of time slices of which the time slice of the event to be inserted is a subset, determining, if the current location is such an intermediate node, if any existing child nodes of said current location are event locations, and if so, adding the event to the proper event location of said current location.

Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed in the antifuse cell opening to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer, and a top electrode disposed over the second barrier metal layer.

Abstract: A thin MCM packaging structure and technique is provided in which a thin film decal interconnect circuit is fabricated on a thin aluminum wafer. The thin-film decal interconnect employs Au metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure. The underside of the decal interconnect structure is provided with metal pads for attachment to conventional aluminum or gold I/O pads on one surface of the integrated circuit die. A thermosonic bonding system is used to bond the die pads to the pads. The aluminum wafer is selectively removed forming one or more cavities to hold one or more die to be mounted on the MCM structure. The die are oriented with their pads in contact with contact pads on the thin-film decal interconnect to which they are bonded and the cavities are filled with a liquid encapsulant and cured.