Abstract: A call party profile presentation system and method for use in a multimedia-capable network for delivering a party's presentation profile to a subscriber at call setup or during the call in order to uniquely identify the party. A multimedia session engine is operable to launch a call treatment application for the subscriber with respect to a call between a call party and the subscriber. Logic associated with the call treatment application determines an appropriate portion of the call party's presentation profile to be provided to the subscriber based on subscriber selection, call party presentation restrictions, or both. A multimedia interface operable with the subscriber's terminal is actuated for delivering an indicium associated with the selected portion of the call party's presentation profile to the subscriber.

Abstract: A memory characterization system and method using a hierarchically-stitched netlist generation technique. A plurality of leaf cells forming a memory instance are generated based on a minimum area required to encompass an optimal number of memory strap points relating to global signals that span the memory instance. Input and output pins are defined for each tile with respect to the global signals in both horizontal and vertical directions. A parametric dataset is obtained for each tile using an extractor (wherein the memory instance is in post-layout condition) or a pre-layout wire-delay estimator. The parametric netlist for the entire memory instance is assembled by coupling the individual parametric datasets using the input and output pins of the tiles with respect to the global signals.

Abstract: A congestion control mechanism for use with a receiver in a telecommunications network using the Service Specific Connection Oriented Protocol (SSCOP). The receiver is disposed in an access network portion of the telecommunications network such that it receives messages from an aggregate portion of the network over an Access Network Interface (ANI) and from a plurality of users over User-Network Interfaces (UNIs) in a distribution network portion. Credit windows granted by the receiver to the transmitters for transmission of message frames are managed by the receiver when it experiences congestion. The congestion control method monitors buffer usage for ANI-based traffic and UNI-based traffic in the receiver by setting appropriate buffer use counters and timers. When the number of available buffers reaches certain predetermined threshold values, the receiver sends an indication to the transmitter to restrict its message transmit window, thereby throttling the message flow therefrom.

Abstract: A product and process for stabilizing Aloe vera gel is disclosed. The process includes the steps of rapidly heating the Aloe vera gel to a temperature in the range of from about 35° C. to about 80° C., adding to the heated Aloe vera gel one or more stabilizing antioxidants, and rapidly cooling the heated Aloe vera gel to a temperature in the range of from about 20° C. to about 30° C. The stabilizing antioxidants may be a tocotrienol/tocopherol blend, rosmarinic acid, polyphenols, or any combination thereof.

Abstract: A semiconductor memory with multiple timing loops for optimizing memory access operations. A clock generator circuit is provided for generating an internal memory clock based on an external clock or an input signal transition supplied to the memory device. The internal memory clock is operable to provide a timing reference with respect to a memory access operation based on a plurality of address signals. A timing loop selector is operable to select a particular timing loop responsive to at least one access margin signal. A shutdown circuit generates an access shutdown signal based on the selected timing loop that is optimized for a memory device of particular size, speed, etc.

Abstract: A node management method and system that supports multiple SNMP agents in a single platform (e.g., a network element or node) with capability to include the AgentX standard. An SNMP master agent and one or more subagents are provided for managing the node, and use the AgentX standard for communication therebetween. At least a select portion of a MIB associated with the management functionality of the managed node is supported by an SNMP peer agent that is proxied via an AgentX subagent (PSA).

Abstract: An apparatus (10) for reducing the likelihood of damaging a semiconductor wafer (18) and the integrated circuit chips of the semiconductor wafer (18) during handling is disclosed. The apparatus (10) comprises a wafer interposer (12) having a wafer receiving portion (28) and a handling portion (30). The wafer receiving portion (28) of the wafer interposer (12) has a plurality of contact pads (22) that are electrically connected and mechanically bonded to the contact pads of the integrated circuit chips of the wafer (18). The handling portion (30) of the wafer interposer (12) extends outwardly from the wafer receiving portion (28) such that the handling portion (30) is accessible to handling equipment without the handling equipment contacting the attached wafer (18).

Abstract: The present invention provides a method and apparatus for testing semiconductor wafers that is simple and allows testing prior to dicing so that the need to temporarily package individual dies for testing is eliminated. As a result, the number of manufacturing steps is reduced, thus increasing first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs. After testing, the wafer is diced into the individual circuits, eliminating the need for additional packaging. One form of the present invention provides an interposer substrate made of a ceramic material that has an upper and a lower surface. There are one or more first electrical contacts on the lower surface and one or more second electrical contacts on the upper surface. There are also one or more electrical pathways that connect the first and second electrical contacts.

Abstract: A system and method for packaging shaped charges (12) for transportation is disclosed. Each shaped charge (12) includes a housing (14) and a liner (16) having a high explosive disposed therebetween. A jet spoiler (20) is positioned proximate the liner (16) of each of the shaped charges (12) to prevent the formation of a jet in the event of an inadvertent initiation of a shaped charge (12). The shaped charges (12) are then oriented in first and second layers such that the jet spoilers (20) positioned proximate the liners (16) of the shaped charges (12) in the first and second layers oppose one another. A shielding panel (22) is disposed between the shaped charges (12) of the first and second layers. The shaped charges (12) including the jet spoilers (20) and the shielding panel (22) are placed within an expandable bag (32) which is in turn enclosed within a transportation container (34).

Abstract: A call treatment system and method in a multimedia-capable network for providing an enhanced call waiting service wherein multiple calls waiting to be serviced are accorded different treatments based on multimedia responses. When a network element serving a subscriber currently engaged in an established call connection with a party receives an indication that an incoming call is being directed towards the subscriber from at least one calling party, a multimedia session engine is invoked by the network element to launch a call treatment application for the subscriber. If the number of calls allowed to wait on the subscriber exceeds a predetermined maximum value, the incoming call is accorded a predetermined default treatment. Otherwise, the call treatment application is operable to query a subscriber profile associated with the subscriber to determine a suitable multimedia interface to be presented for effectuating a response using a browser-based interactive system.

Abstract: A portable induction heating system which utilizes a broadband high frequency high-power, low output impedance power generator formed from switching MOSFET devices. A voltage-controlled oscillator (VCO) or microprocessor-controlled signal generator drives a power output stage under feedback control so as to effectuate resonance at a high frequency in an induction coil assembly connected to the power generator. The power generator is operable with a switching regulator that can supply a fixed DC voltage, e.g., 12 to 48 V or a variable setpoint. The induction coil assembly includes a capacitive circuit portion connected to a conductive coil that can couple magnetic field to a susceptor. A microcontroller is provided for inputting operating parameters such as power, frequency, duty cycle and duration, and is operable to auto-tune the VCO output under feedback control by sweeping frequency at startup as well as by controlling drift during operation under a changing load.

Abstract: Self-referenced, built-in access shutdown mechanism for a memory circuit. Instead of using a separate reference decoder/driver block and reference wordline path in the access timing loop, a wordline selected for accessing a core cell itself is utilized for referencing a shutdown sequence. A pair of complementary reference bitlines (BLS and BLE) are operable with a column of reference cells disposed in the row decoder. BLS/BLE control logic circuitry is operable to fine-tune the WL pulse width so as to minimize dead time and power consumption in access cycle operations.

Abstract: A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. Each memory location is addressable by a row address and a column address. The data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.

Abstract: A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.

Abstract: A matched set of integrated circuit chips (74, 78) and a method for assembling such integrated circuit chips (74, 78) into a matched set are disclosed. A first semiconductor wafer (62) having a plurality of integrated circuit chips (74) of a first type and a second semiconductor wafer (64) having a plurality of integrated circuit chips (78) of a second type are electrically and mechanically coupled to an interposer (52) to form a wafer-interposer assembly (50). The integrated circuit chips (74, 78) of the first and second wafers (62, 64) are then tested together. The wafer-interposer assembly (52) is then diced into a plurality of chip assemblies having chips (74) of the first type and a plurality of chip assemblies having chips (78) of the second type. Based upon the testing, at least one of the chip assemblies having chips (74) of the first type and at least one of the chip assemblies having chips (78) of the second type are selected for inclusion in the matched set.

Abstract: The present invention provides a wafer interposer for electrical testing and assembly into a conventional package. The present invention provides an interposer comprising a support having an upper and a lower surface. One or more solder bumps are on the lower surface. One or more first electrical terminals are on the upper surface, substantially corresponding to the position of the solder bumps, and forming a pattern. One or more first electrical pathways pass through the surface of the support and connect the solder bumps to the first electrical terminals. One or more second electrical terminals are on the upper surface of the support. The second electrical terminals are larger in size and pitch than the first electrical terminals, and they are located within the pattern formed by the first electrical terminals. One or more second electrical pathways connect the first electrical pathways to the second electrical pathway.

Abstract: The present invention provides a method, apparatus and system for building a wafer-interposer assembly. The method includes the steps of forming a redistribution layer (RDL) pad on a semiconductor wafer. The semiconductor wafer has a semiconductor die and the RDL pad has an electrical connection to the semiconductor die. A layer of epoxy is placed on the semiconductor wafer and on the RDL pad. The epoxy is then leveled generally parallel to the surface of the semiconductor wafer and removed from a portion of the RDL pad. An interposer pad is formed on the RDL pad where the epoxy was removed.

Abstract: A matched set of integrated circuit chips (74, 78) and a method for assembling such integrated circuit chips (74, 78) into a matched set are disclosed. A first semiconductor wafer (62) having a plurality of integrated circuit chips (74) of a first type and a second semiconductor wafer (64) having a plurality of integrated circuit chips (78) of a second type are electrically and mechanically coupled to a pair of interposers (52, 53) to form a pair of wafer-interposer assemblies (50, 51). The integrated circuit chips (74, 78) of the first and second wafers (62, 64) are then tested together. The wafer-interposer assemblies (52, 53) are then diced into a plurality of chip assemblies having chips (74) of the first type and a plurality of chip assemblies having chips (78) of the second type. Based upon the testing, at least one of the chip assemblies having chips (74) of the first type and at least one of the chip assemblies having chips (78) of the second type are selected for inclusion in the matched set.

Abstract: A chip assembly (162) with integrated power distribution between an integrated circuit chip (164) and a section of wafer interposer (166) is disclosed. The wafer interposer section (166) has first (80, 82) and second (86, 88) sets of contact pads that are electrically and mechanically coupled to first and second sets of contact pads of the integrated circuit chip (164). The wafer interposer section (166) has first (32) and second (36) supply voltage terminals that are respectively coupled to the first (80, 82) and second (86, 88) sets of contact pads of the wafer interposer section (166) that provide first and second supply voltages to the first and second sets of contact pads of the integrated circuit chip (164), thereby integrating power distribution between the integrated circuit chip (164) and the wafer interposer section (166).