Abstract: An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: A static random access memory (14) has a normal mode of operation and a low voltage mode of operation. A memory array (15) includes memory cells (16) coupled to a first power supply node (VDD) for receiving a power supply voltage. A plurality of word line drivers is coupled to word lines of the memory array (15) and to a second power supply node (37). A word line driver voltage reduction circuit (36) has an input coupled to the first power supply node (VDD) and an output coupled to the second power supply node (37) for reducing a voltage on the output in relation to a voltage on the input in response to a low power supply voltage signal, and thus improving a static noise margin of the memory cells (16).

Abstract: A data processing system (30) includes two processors (70, 80) and a serial data controller (36) for selectively multiplexing serial data signals between one or more of a plurality of serial data devices (40, 42, 44, 46, 74, 76, 82) The serial data controller (36) includes one or more host ports (50, 52, 54) and one or more peripheral ports (56, 58, 60, 62) coupled together through a switching matrix (64). A control circuit (66) and a plurality of control registers (68) are used to configure and control a serial data path created between two or more ports including clock and frame synchronization timing of the data path.

Abstract: A power transistor, formed from transistors connected in parallel, each transistor is formed in an active region using a relatively long gate called a gate finger that is typically formed from polysilicon that accumulates resistance over its length. To alleviate this, the gate finger is strapped to a metal line at tabs adjacent to the finger gate over the active area, typically over the source, but the tabs add gate-to-source capacitance. This was previously quite small but as gate dielectrics have gotten thinner there is more capacitive coupling to the substrate by the tabs, and as gates have gotten thinner there is more resistance in the polysilicon finger gates. Both have the effect of increasing the RC time constant of the gate finger. This increase in RC time constant is alleviated by increasing the thickness of the dielectric separating the tabs from the substrate thereby reducing the capacitance caused by the tabs.

Abstract: A method for creating a vertical double-gate transistor design includes providing a planar transistor layout (10) having a gate layer (12) overlying an active layer (14). In one embodiment, a first intermediate layer (18) is defined based on an overlapping region of the gate and active layers, and, using the first intermediate layer, a second intermediate layer (22) is defined which defines a spacing between at least two fins of the vertical double-gate transistor design. The second intermediate layer may also define a length and a width of the at least two fins. One embodiment modifies a dimension of the first intermediate layer prior to defining the second intermediate layer. The method further includes defining a resulting layer (24) based on a non-overlapping region of the second intermediate layer and the active layer. The resulting layer may then be used to create a mask and a semiconductor device (30) corresponding to the vertical double-gate transistor design.

Abstract: A radio receiver (100) has an equalizer (500) that operates in the time domain to remove residual interference that is not removed by an IF filter (200) operating in the frequency domain that is caused by an adjacent interfering FM station. The equalizer (500) includes a modified constant modulus algorithm (CMA) to generate a tap update signal from the output of the equalizer (500). The equalizer (500) uses the modified CMA to reduce an amplitude fluctuation of the received signal caused by the adjacent interfering station. The CMA is modified to use an infinite impulse response (IIR) filter (540) to generate the tap update. The IIR filter (540) also speeds up a convergence of the modified CMA to provide better performance.

Abstract: A double gate semiconductor device (2006) is used beneficially as a multiplier (2000). The double gate semiconductor device (2006) has a lateral fin (105) as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between the two gates. To increase drive current, multiple transistors are easily connected in parallel by having a continuous fin structure (2106) with alternating source/drain terminals (2120, 2122, 2124, 2126) in which the sources are connected together and the drains are connected together. Gates (2116, 2110) are positioned between each pair of adjacent source/drain terminals and electrically connected together. The multiplier (2000) may also be used as a mixer and further as a phase detector.

Abstract: An ESD protection circuit (201) is for use with a high-voltage tolerant I/O circuit in an IC. This is accomplished by providing a small ESD diode (217) from the I/O pad to a relatively small boosted voltage bus (BOOST BUS). The BOOST BUS is used to power a trigger circuit (203). This path has very little current flow during an ESD event due to minimal current dissipation in the trigger circuit. There is a diode drop but only very little IR voltage drop from the I/O pad to the trigger circuit (203). The trigger circuit (203) controls relatively large cascoded clamp NMOSFETs (207, 209). The net result is that a gate-to-source voltage (VGS) of both of the clamp NMOSFETs is increased thus increasing the conductivity of the cascoded clamp NMOSFETs (207, 209). This reduces the on-resistance of each of the NMOSFETS (207, 209), thereby improving the ESD performance, and reducing the layout area required to implement robust ESD protection circuits.

Abstract: A radio receiver (100) has an IF (intermediate frequency) filter (200) for automatically adjusting its intermediate frequency. The filter (200) includes a filter bank (304), an accumulative sub-band formation (322) and an accumulative sub-band power estimator/switch control (324). The filter bank (304) generates sub-bands, each sub-band having a predetermined frequency range. The accumulative sub-band formation (322) selectively sums the sub-bands to provide lowpass filters having incrementally increasing bandwidth. Power estimates of the lowpass filters are used to determine which lowpass filter output is appropriate for adjacent station interference. Also, if there is no adjacent station interference, the IF filter (200) selects the appropriate filter output depending on the signal strength of the desired station.

Abstract: A non-volatile memory (10) includes at least two buried bit lines (45, 47) formed within a semiconductor substrate (12), a charge storage layer (18) overlying the semiconductor substrate (12); a control gate (26) overlying the charge storage layer (18); an insulating liner (30) overlying the control gate; and first and second conductive sidewall spacer control gates (32, 34). Multiple programmable charge storage regions (42) and (41, 44) are created within the charge storage layer (18) beneath respective ones of the control gate (26) and the first and second sidewall spacer control gates (32, 34). Also, the non-volatile memory (10) is a virtual ground NOR type multi-bit flash EEPROM (electrically erasable programmable read only memory). By using conductive sidewall spacers as the control gates, a very dense multi-bit non-volatile memory can be manufactured.

Abstract: In one embodiment, a method (50) is provided for improving switched capacitor performance by lowering a mismatch constraint to be equal to, or nearly equal to, a noise constraint. The mismatch constraint is lowered by increasing a finger spacing of a fringe capacitor design (10) while maintaining the same surface area covered by the fringe capacitor design (10). In another embodiment, a noise constraint is lowered by decreasing finger spacing. Lowering the noise constraint by decreasing finger spacing reduces the area of a fringe capacitor used in, for example, an analog-to-digital converter. Both embodiments may improve performance of the analog-to-digital converter by lowering power consumption, increasing speed, or both.

Abstract: A memory (10) includes a variable refresh control circuit (20) for controlling the refresh rate of a memory array (12) using a capacitor for data storage. In one embodiment, each test cell of a plurality of test memory cells (30, 32, 34, and 36) is refreshed at different rates. A monitor circuit (18) is provided for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting the refresh rate of the memory array (12). In another embodiment, a variable refresh control circuit (20?) includes a plurality of test memory cells (70, 72, 74, and 76) that are all refreshed at the same rate but each of the test memory cells (70, 72, 74, and 76) is implemented to have a different charge storage capacity than the other test memory cells. The monitor circuit (18) monitors the stored logic state of each of the plurality of test memory cells (70, 72, 74, and 76), and in response, adjusts a refresh rate of the memory array (12).

Abstract: A packaged semiconductor device (20) has a first integrated circuit die (28) having a top surface with active electrical circuitry implemented thereon. The first die (28) is mounted in a cavity (21) of a first heat spreader (22). A second die (36) having electrical circuitry implemented on a top surface is attached to the top surface of the first die (28). Both of the die (28 and 36) are electrically connected to a substrate (24) mounted on the first heat spreader (22). A second heat spreader (40) is mounted on the top surface of the second die (36). The second heat spreader (40) provides an additional path for thermal dissipation of heat generated by the second die (36).

Abstract: A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

Abstract: An integrated circuit (10) includes a multiple voltage digital multiplexer circuit (30) for multiplexing digital signals provided at different supply voltage levels. In one form, the multiplexer (30) includes an analog multiplexer (32) for receiving the digital signals, a level shifter (40) coupled to the output of the analog multiplexer (32), and a supply voltage multiplexer (34) for providing one of various supply voltages used on the IC corresponding to the signals being multiplexed. A control circuit (38, 39) is used to control the input selection of the analog multiplexer (32) as well as the supply voltage multiplexer (34) for providing the correct supply voltage to the level shifter (40). This provides the ability to multiplex digital signals of differing voltage levels onto a single pad on the IC (10).

Abstract: An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (21) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.

Abstract: A package substrate (12, 52) has a first surface, a second surface opposite a first surface, and a cavity (22, 70) formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die (20, 60) is placed in the cavity, and a conductive material (24, 72) is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer (28, 78) may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.

Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).