Patents Represented by Attorney, Agent or Law Firm Daniel P. Morris
  • Patent number: 8157158
    Abstract: A solder joint comprising a solder capture pad on a substrate having a circuit; and a lead containing or a lead free solder selected from the group comprising Sn—Ag—Cu solder, Sn—Cu solder and Sn—Ag solder adhered to the solder capture pad; the solder selected from the group comprising between 0.1 and 6.0 per cent by weight Zn. A solder joint, comprising a solder capture pad on a substrate having a circuit; and a Sn—Cu lead free solder adhered to the solder capture pad, the solder comprising between 0.1 and 6.0% by weight Zn. Formation of voids at an interface between the solder and the solder capture pad is suppressed. A method for forming solder joints using the solders.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: April 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Donald W. Henderson, Sung K. Kang, Da-Yuan Shih
  • Patent number: 8081280
    Abstract: In a liquid crystal display device, a method for creating desirable pretilt angle by means of topography of the substrates, such as a surface that is sloped with respect to the surface of the electrodes. In combination with a low pretilt but highly photo-stable alignment layer, which may be very resistant to high levels of ultraviolet radiation, a high pretilt and photo-stable alignment structure is generated, by essentially combining two incompatible technical approaches. The ever more stringent requirements for projection displays are met. The methods for producing such sloped surfaces and the considerations related to design of the sloped surfaces are disclosed.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: George Liang-Tai Chiu, Steven Alan Cordes, James Patrick Doyle, Matthew J. Farinelli, Minhua Lu, Hiroki Nakano, Ronald Nunes, James Vichiconti
  • Patent number: 8080876
    Abstract: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, John U. Knickerbocker, Michelle L. Steen, Cornelia K. Tsang
  • Patent number: 8060169
    Abstract: A new class of superconducting compositions, and methods for making and using them are described. These compositions exhibit superconductivity at temperatures in excess of 26° K. and are comprised of transition metal oxides having at least one additional element therein which may create a multi-valent state of the transition metal oxide. The composition can be a ceramic-like material having a layer-like crystalline structure, where the structure is distorted having either an oxygen excess or deficiency. An example is RE-AE-TM-O, where RE is a rare earth or rare earth-like element, AE is an alkaline earth element, TM is a transition metal element (such as Cu) and O is oxygen.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Johannes Georg Bednorz, Carl Alexander Mueller
  • Patent number: 8051878
    Abstract: An apparatus for performing multi-dimensional assays using a microfluidic chip is presented. The apparatus comprises of two crossing series of micro-channels on the microfluidic chip. The apparatus further comprises of a plurality of magnetic valves placed at the crossings and a guiding magnet. When an operator places the guiding magnet in a vicinity of the chip, the guiding magnet produces a proximal magnetic field gradient at a location of each of the plurality of magnetic valves. At the first micro-channel crossing, a magnetic valve controls fluid flow in the first micro-channel, and another magnetic valve controls fluid flow in the second micro-channel at the first micro-channel crossing. Each magnetic valve comprises a magnetic bead and a cavity on the chip next to a corresponding micro-channel section.
    Type: Grant
    Filed: December 6, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Emmanuel Delamarche
  • Patent number: 8026613
    Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: September 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Balaram Ghosal, Sung K. Kang, Stephen Kilpatrick, Paul A. Lauro, Henry A. Nye, III, Da-Yuan Shih, Donna S. Zupanski-Nielsen
  • Patent number: 8018818
    Abstract: Systems and methods for storing and reading data in a data storage system are provided. The data storage system includes a storage medium for storing data. The storage medium stores data as a plurality of topographical features. Further, the data storage system includes one or more transducer. One or more transducer writes data on the storage medium. Additionally, the data storage medium includes one or more gates. A first voltage bias is applied to one or more gates. The data storage system further includes, one or more read heads. One or more read heads include one or more Floating Gate Transistors (FGTs). The first voltage bias creates an electric field between one or more FGTs and one or more gates. A change in the electric field is detected by one or more FGTs.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mark Alfred Lantz, Bernd W Gotsmann
  • Patent number: 7968450
    Abstract: Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Satyanarayana V. Nitta, Sampath Purushothaman
  • Patent number: 7923849
    Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Balaram Ghosal, Sung K. Kang, Stephen Kilpatrick, Paul A. Lauro, Henry A. Nye, III, Da-Yuan Shih, Donna S. Zupanski-Nielsen
  • Patent number: 7855101
    Abstract: A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: December 21, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bruce K. Furman, Sampath Purushothaman, Muthumanickam Sankarapandian, Anna Topol
  • Patent number: 7741834
    Abstract: Method for detecting and reporting a condition. The components of the invention include an electronic package having a substrate with electrically conducting lines electrically connected to an integrated chip, and to a source of voltage. The integrated circuit chip is mounted onto a substrate and electrically connected to at least one electrically conducting line. A sensor, combined with a signal generator, connected to the substrate, is operable to generate an electrical signal upon detection of a condition selected from a condition of the substrate and a condition of an electrical connection to the substrate. The signal generator, after immediately receiving the aforesaid electrical signal from the sensor, emits the warning signal. The warning signal of indicated of an existing defect or a condition which can lower the longevity of the total electronic package.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: June 22, 2010
    Assignee: International Business Machines Corporation
    Inventors: Hien Dang, Sri Sri-Jayantha
  • Patent number: 7687913
    Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.
    Type: Grant
    Filed: February 19, 2007
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Nirupama Chakrapani, Matthew E. Colburn, Christos D. Dimitrakopoulos, Dirk Pfeiffer, Sampath Purushothaman, Satyanarayana V. Nitta
  • Patent number: 7649153
    Abstract: In one aspect the invention provides a method for laser induced breakdown of a material with a pulsed laser beam where the material is characterized by a relationship of fluence breakdown threshold (Fth) versus laser beam pulse width (T) that exhibits an abrupt, rapid, and distinct change or at least a clearly detectable and distinct change in slope at a predetermined laser pulse width value. The method comprises generating a beam of laser pulses in which each pulse has a pulse width equal to or less than the predetermined laser pulse width value. The beam is focused above the surface of a material where laser induced breakdown is desired.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Richard Alan Haight, Peter P. Longo, Daniel Peter Morris, Alfred Wagner
  • Patent number: 7613368
    Abstract: Integrated optoelectronic chips or collections of chips on a module that have both electrical as well as optical interconnects offer many advantages in speed, power consumption and heat generation. Mixed signal types, however, pose significant packaging challenges. This invention describes a land grid array (LGA) interposer which can simultaneously connect electrical and optical signals from a module to a printed circuit board.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: November 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Gareth G. Hougham, Russell A. Budd, Punit P. Chiniwalla, Paul W. Coteus, Alphonso P. Lanzetta, Frank R. Libsch
  • Patent number: 7598169
    Abstract: A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: October 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Elbert E. Huang, Christy S. Tyberg, Ronald A. DellaGuardia
  • Patent number: 7546670
    Abstract: A method to fabricate a high density, minimal pitch, thermally matched contactor assembly to maintain electrical contact with contact regions on fully processed semiconductors, preferably while still in wafer form, and throughout a range of temperatures. A guide plate and a contactor assembly for such use, comprising a substrate formed of a material having a coefficient of thermal expansion approximately equal to that of the device; and at least one hole in the guide plate for receiving an electrical contact (probe element) for contacting at least one respective region on said surface, said at least one hole being sized and shaped so as to accept said electrical contact, while allowing said electrical contact (probe element) to move with respect to said hole in said guide plate. The material can be one of silicon, borosilicate glass and cordierite.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: June 16, 2009
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Dalton, Anna Karecki, legal representative, Samuel R. McKnight, George F. Walker, Simon M. Karecki
  • Patent number: 7538565
    Abstract: A high density test probe which provides an apparatus for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: May 26, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Patent number: 7523852
    Abstract: Improved interconnects are produced by injection molded solder which fills mold arrays with molten solder so that columns that have much greater height to width aspect ratios greater than one are formed, rather than conventional flip chip bumps. The columns may have filler particles or reinforcing conductors therein. In the interconnect structures produced, the cost and time of a subsequent underfill step is reduced or avoided. The problem of incompatibility with optical interconnects between chips because underfills require high loading of silica fillers which scatter light, is solved, thus allowing flip chips to incorporate optical interconnects.
    Type: Grant
    Filed: December 5, 2004
    Date of Patent: April 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Stephen L. Buchwalter, Claudius Feger, Peter A. Gruber, Sung K. Kang, Paul A. Lauro, Da-Yuan Shih
  • Patent number: 7495342
    Abstract: A method is described having the steps of providing a surface having a plurality of wire bondable locations, wire bonding a wire to each of the wire bondable locations using a wire capillary tool; controlling the position of the capillary tool with respect to the substrate; after forming a wire bond of the wire to the wire bondable location moving the capillary tool relative to the surface as the capillary tool is moved away from the surface to form a wire having a predetermined shape.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: February 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Da-Yuan Shih
  • Patent number: 7477567
    Abstract: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to the storage cell for selectively changing the temperature of the changeable magnetic region of said storage cell. By heating the storage cell via the heating element, as opposed to heating the storage cell by directly applying current thereto, more flexibility is provided in the manufacture of the storage cells.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: January 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Philip L. Trouilloud