Abstract: A self-aligned process for fabricating a GaAs semiconductor MESFET by depositing a layer of tungsten over the GaAs substrate, and ion implanting the substrate to provide channel doping. A gate composed of a conductive refractory material is deposited and delineated on the tungsten layer, and source and drain regions are formed in the substrate using the gate as a mask. The resulting device is annealed and contacts are formed to the source and drain regions, and to the gate.
Abstract: A semiconductor laser diode which operates in an extended optical cavity in conjunction with a negative resistance device such as a Gunn diode for sustained mode-locked operation. The circuit is capable of generating high repetition rate picosecond optical pulses and is suitable for monolithic or hybrid implementation.
Abstract: A process for fabricating a semiconductor device or a semiconductor substrate having a first major surface on which active semiconductor devices are to be formed, and a second major surface. An etch stop layer is provided on the first major surface. A layer of semiconductor material is deposited on the etch stop layer and portions of the substrate are selectively removed to provide a pattern of apertures in the layer extending to the etch stop layer. Dopant species are provided through the second major surface to form active regions in the layer of semiconductor material.
Abstract: A frequency multiplier circuit for producing higher order harmonics of an input frequency is disclosed. The frequency multiplier circuit comprises a multiple quantum well semiconductor device which is used to couple energy from an input circuit tuned to the input frequency to an output circuit which is tuned to a desired higher order harmonic of the input frequency.
Abstract: In a data communications network having a plurality of information processing sytems coupled to a communication channel which serially transmits data in the form of information packets, a network controller is provided between the communication channel and an information processing system. The network controller includes a counter connected to the transmit buffer for controlling the release of packets from the transmit buffer according to a predetermined amount of time between the transmission of successive packets.
Abstract: A network controller includes an interface unit connected to a communication network channel for transferring data in the form of information packets to and from the channel; a receive buffer connected for storing in parallel form the data packets transferred from the communication channel; and first and second shift registers having n bit positions including a pointer bits to the receive buffer, circulating at different clock rates corresponding to the clock rate of data on said communication channel and the clock rate of the system bus.
Abstract: A signal processing device for the correction of signal amplitude distortion occurring in a plurality of signalling channels such as obtained from a detector array in which each detector has a different non-uniform response. Compensatory amplitude adjustment is made to each sampled signal in accordance with the statistical deviation of the signal from a preselected statistical model. A signal sampling device employs each sampled signal as a write-address for generating a statistical amplitude distribution function. Inverse distribution function means, responsive to addressing by the distribution function, provides an output signal of compensatorily modified amplitude for each signal sample.
Abstract: A method of quantitatively measuring the relative alignment of elements on a surface of a semiconductor body formed by two sequential masking steps during processing is provided. A fixed pattern of rectangular images are formed on a first mask; and a fixed pattern of repeating U-shaped images are formed on a second mask. The semiconductor body is processed so that the rectangular images on the first mask align with the U-shaped images on the second mask. An electrical probe is applied to opposed ends of the boustrophederal pattern formed and the electrical resistance measured to determine a parameter related to the relative alignment of elements on the semiconductor body.
Abstract: A semiconductor integrated circuit is described which includes an array of electronic devices and a plurality of electronic access devices. The access devices consist of sets of MOSFETs which may be turned on by the joint action of X and Y address lines to permit individual and isolated electrical connection between selected electronic devices in the array and peripheral on or off-chip sensing circuits. This permits continuous readout to be established and maintained for the selected devices without interference with the other devices in the array and without a requirement to readout any but the selected devices. One important embodiment of the present invention is one in which the electronic devices are visible or infrared radiation detectors. In order to provide minimum dead space between the array detectors, the array and access devices may be disposed on opposite surfaces of the semiconductor body.
Abstract: A method of fabricating a semiconductor integrated circuit by providing a semiconductor body having a major surface; depositing a first layer of a conductive material on the major surface of the semiconductor body, and depositing a layer of a refractory silicide on the first layer of conductive material. Portions of said refractory silicide layer are marked to define a first pattern thereon; and the silicide layer is etched down to the first conductive layer in order to produce the pattern defined by the masking step. Portions of the body are masked again to define a second pattern thereon; etching said first conductive layer in said second masking pattern. The semiconductor body is sintered to stabilize the contact between first conductive layer and layer of refractory silicide. A layer of dielectric material is deposited on body. Portions of said dielectric material are masked to define a third pattern thereon; and the dielectric material is etched to silicide layer in accordance with the third pattern.
Abstract: A digital data processor adapted to be responsive to an applied signal input (x.sub.n) for generating an output signal indicative of a preselected function of the signal input, and comprising signal sampling memory means adapted to be responsive to an alternate one of the applied input signal and a clocked counter output as a read/write-address for generating a statistical amplitude density function d(x) representing the number of occurrences of an amplitude of a sampled input x. Digital attenuating means is interposed between a read-out and read-in of said memory means during sampling intervals in which said memory means is responsive to said clocked counter output for low-pass filtering the amplitude density function as to be dependent of the size of the sampled population of the sampled signal (x.sub.n).
Abstract: A semiconductor integrated circuit using charged coupled device (CCD) technology for performing demodulation of time-varying signals which have been phase or amplitude modulated. The CCD circuit performs a sampling of the time-varying signal at a suitable sampling frequency depending upon the frequency of the phase or amplitude modulation of the carrier. The CCD device converts the sample into an equivalent charge packet which is used to control the control electrode of a field effect transistor in an amplifier circuit. The magnitude of the sample is representative of the amplitude of the carrier so that the output of the field effect transistor represents a demodulated signal. The circuit is a broad spectrum device, operable with a signal frequency from the audio into the gigaHertz (GHz) frequency range.
Abstract: A light emitting bipolar transistor, adapted to produce light from cathodoluminescence, upon being biased into conduction, the light emitting bipolar transistor being formed on the top surface of a relatively flat semiconductor substrate and having active regions comprising: a collector region, and an emitter region, the collector and emitter regions being of a first conductivity type, and an extended base region of a second conductivity type, the extended base region being interposed between the collector and the emitter regions, and the base region having a coatable surface, a phosphor coating, the phosphor coating covering the base region coatable surface, and respective connections to the collector emitter and base regions; whereby, biasing the transistor into conduction produces an electric field in the base region, the electric field in the base field inducing electrons in the base region to increase energy to a high energy level and to drift, some drifting high energy electrons being scattered into the
Abstract: A digital signal bypass circuit including a two terminal clock input for supplying a clock input signal with a predetermined first frequency. A divide-by-two squaring circuit is also provided which is input for synchronously translating the clock input signal into an output signal having a frequency one-half of the predetermined first frequency. A bypass circuit is provided which is connected to the clock input and responsive to the clock input signal applied thereto, the bypass circuit being operative to disable the divide-by-two squaring circuit so that the output signal has a frequency equal to the predetermined first frequency.
Abstract: A shielded amplifier adapted for use with an infrared detector array mounted on a focal plane and operating in a cryogenically cooled environment and adapted to receive a signal output from a high impedance signal source, the shielded amplifier being required to amplify the signal with relatively uniform gain over a predetermined bandwidth comprising a base substrate of semiconductor material, an integrated amplifier circuit means formed on the base substrate, a resistor connected for negative feedback between the output terminal and the input terminal, a conductive shield interposed between the resistor and the integrated amplifier circuit means, a first insulating means for insulating the resistor from the conductive shield, a second insulating means for insulating the conductive shield from the integrated circuit amplifier means; whereby the conductive shield is disposed to reduce stray parasitic capacitance thereby increasing the shielded amplifier uniform gain over a predetermined bandwidth.
Abstract: An infrared lens system for projecting an image from object space onto a flat image plane, the lens system being corrected over the spectral region of 3.3 to 4.2 microns and having a selectable narrow field of view comprising: an objective lens system having a plurality of lens elements formed of material optically transparent over the spectral region of 3.3 to 4.2 microns, the plurality of lens elements being coaxially aligned and adapted to receive light from object space and to form an image on the flat image plane, a selectable afocal telescope, the selectable afocal telescope being in select field of view determining relation with the objective lens system, whereby upon selection, the selectable afocal telescope cooperates with the objective lens system to provide a narrow field of view.
Abstract: An ac coupled, chopper stabilized differential comparator circuit characterized receiving a differential signal voltage applied between a signal input terminal and a reference signal input terminal, providing differential outputs at a first and second differential output terminal and being characterized as operating from a voltage source with respect to a reference potential comprising: amplifier means, characterized by a first stage differential amplifier having, a first channel amplifier having an input terminal and an output terminal. The first channel amplifier output terminal is connected to the first differential output terminal. The first stage differential amplifier also has a second channel amplifier having an input terminal and an output terminal. The second channel amplifier output terminal is connected to the second differential output terminal. The gain of the second channel amplifier is essentially equal to the gain of the first channel amplifier.
Abstract: There is disclosed a computer system including a storage means such as a random access memory (RAM) for receiving data to be displayed upon a display means, e.g. a color cathode ray tube, a microprocessor for control of the computer system operations, and viewer input devices such as a control stick or keyboard, whereby the viewer may respond selectively to the data displayed upon the display means. A limited capacity storage unit, illustratively in the form of a tape cassette, stores data in the form of a program for permitting the viewer to store useful material in the form of a repository, such as a Christmas list; the program to be displayed by the display means can assume any of a limitless number of programs and may be adapted to an exceptionally wide range of uses for the home, office or school. The computer system permits the viewer to respond as through the input devices, to the material being displayed, whereby subsequent material may be effected.
July 15, 1982
Date of Patent:
November 13, 1984
Rockwell International Corporation
David J. Mueller, Daniel G. Prysby, John V. Moravec, George A. Watson