Patents Represented by Attorney Darby & Darby PC
  • Patent number: 7443905
    Abstract: A method and apparatus for spread spectrum clock generation is provided. Modulation of the clock signal may be accomplished with an N/N?1 clock divider. The N/N?1 clock divider is configured to divide the clock signal by N or N?1, depending on the carry output signal of an accumulator circuit. The accumulator circuit is configured to provide the carry output signal in response to a modulating waveform signal. The modulating waveform signal may be a triangle wave, a sinusoidal wave, another waveform appropriate for spread-spectrum clock generation, and the like.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: October 28, 2008
    Assignee: National Semiconductor Corporation
    Inventors: William Llewellyn, Ha Chu Vu
  • Patent number: 7442339
    Abstract: Disclosed herein are methods, apparatuses, and systems for performing nucleic acid sequencing reactions and molecular binding reactions in a microfluidic channel. The methods, apparatuses, and systems can include a restriction barrier to restrict movement of a particle to which a nucleic acid is attached. Furthermore, the methods, apparatuses, and systems can include hydrodynamic focusing of a delivery flow. In addition, the methods, apparatuses, and systems can reduce non-specific interaction with a surface of the microfluidic channel by providing a protective flow between the surface and a delivery flow.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Narayanan Sundararajan, Lei Sun, Yuegang Zhang, Xing Su, Selena Chan, Tae-Woong Koo, Andrew A. Berlin
  • Patent number: 7440476
    Abstract: A method and apparatus for providing a technique to transfer two digital video signals synchronously across a bus sharing the same pixel clock and data bus.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: October 21, 2008
    Assignee: Zoran Corporation
    Inventor: Gerard Yeh
  • Patent number: 7440813
    Abstract: A method of manufacturing electronic circuits including generating CAD data, a bill of materials and an approved component vendor list for an electronic circuit and employing the CAD data, the bill of materials and the approved component vendor list for automatically generating a pick & place machine-specific component loading specification, a pick & place machine-specific component placement sequence and pick & place machine-specific component data for governing the operation of at least one specific pick & place machine in a manufacturing line.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: October 21, 2008
    Assignee: Valor Computerized Systems Ltd.
    Inventors: Bini Elhanan, Tovi Yadin, Michael Parker, Henry Jurgens, Nadav Pilnick, Mikko Puranen, Tero Laakso
  • Patent number: 7441045
    Abstract: A system and method for balancing the load on virtual servers managed by server array controllers at separate data centers that are geographically distributed on a wide area network such as the Internet is described. The virtual servers provide access to resources associated with a domain name request by a client program. When a Primary Domain Name System (DNS) determined the requested domain name is delegated to a EDNS, the EDNS employs metric information and statistics to resolve an IP address for a virtual server that is selected by the EDNS to optimally balance the load and provide access to resources associated with the domain name. The EDNS may load balance name servers. Additionally, the name server load balancing system may bridge disparate content delivery networks. Internet addresses are divided into geographical information that is used to delegate traffic. Also, metric information is collected and analyzed to help distribute the traffic.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: October 21, 2008
    Assignee: F5 Networks, Inc.
    Inventors: Bryan D. Skene, Scott P. Tennican, Thomas E. Kee
  • Patent number: 7439810
    Abstract: RF amplifier bias system for TDMA application. A bias circuit (200) is coupled to an RF power amplifier (201) circuit. The bias circuit includes a charge pump/sink circuit (215) a voltage reference circuit (204) and voltage scaling circuit (208, 210, 214). The bias system provides fast response time when transitioning between various bias voltage applied to an FET RF transistor (244).
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: October 21, 2008
    Assignee: Harris Corporation
    Inventors: Anthony Manicone, Matthew Harris
  • Patent number: 7435228
    Abstract: Method for accurately measuring hearing loss includes the steps of selecting a series of audio tones within the normal range of hearing (502) and then measuring a relative sensitivity of a test subject with respect to the ability to hear each of the audio tones, exclusive of the effects of tinnitus. (504, 506, 508, 510, 512) The relative sensitivity of the test subject to hear the tones can be measured by determining (510) for each tone an intensity necessary for the test subject to hear the tones at a subjectively equal loudness level which is selected to exceed a perceived level of noise attributable to tinnitus for the test subject.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: October 14, 2008
    Assignee: Harris Corporation
    Inventor: G. Patrick Martin
  • Patent number: 7435430
    Abstract: Disclosed is a natural sedative composition for the treatment of insomnia, anxiety, stress and all kinds of sleep disorders, the composition comprising extract of plant Myristica fragrans and/or plant Hedychium spicatum and a pharmaceutically acceptable carrier. Also disclosed are methods for obtaining the plant extract and dosage forms.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: October 14, 2008
    Assignee: MMI Corporation
    Inventors: Shankar Kumar Mitra, Ekta Saxena, Marikunte Venkata Ranganna
  • Patent number: 7437656
    Abstract: A method for recoding an input sequence of words, including assigning a respective bit-grade to at least one of the bits in a first word in the input sequence, deriving candidate words from the first word in response to the respective bit-grade, and inserting one of the candidate words into each of a plurality of candidate sequences, so that each of the candidate sequences contains one of the candidate words. The method further includes adding subsequent words to the candidate sequences, the subsequent words consisting of a further candidate word derived from a further word in the input sequence, computing respective sequence parameters for the candidate sequences, based on a relation between the candidate words and the subsequent words in the candidate sequences, selecting one of the candidate sequences in response to the sequence parameters, and outputting one of the candidate words contained in the selected candidate sequence.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: October 14, 2008
    Assignee: Mysticom Ltd.
    Inventors: Eyran Lida, Boaz Shahar
  • Patent number: 7432113
    Abstract: The present invention is based on the discovery that the methods described herein for the production of metallic colloids result in colloids exhibiting increased signal enhancement and reproducibility for the SERS detection of biomolecules. Thus, using the methods of the invention, a wide variety of biomolecules can be detected with a greater sensitivity and reliability.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: October 7, 2008
    Assignee: Intel Corporation
    Inventors: Tae-Woong Koo, Selena Chan, Xing Su, Jingwu Zhang, Lei Sun
  • Patent number: 7432112
    Abstract: The present invention is based on the discovery that the methods described herein for the production of metallic colloids result in colloids exhibiting increased signal enhancement and reproducibility for the SERS detection of biomolecules. Thus, using the methods of the invention, a wide variety of biomolecules can be detected with a greater sensitivity and reliability.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: October 7, 2008
    Assignee: Intel Corporation
    Inventors: Tae-Woong Koo, Selena Chan, Xing Su, Jingwu Zhang, Lei Sun
  • Patent number: 7432671
    Abstract: A level-shifting inverting circuit provides a blanking signal to Grid 1 of a CRT. The circuit provides the blanking signal from a blanking logic signal according to a voltage transfer characteristic that is substantially similar to the voltage transfer characteristic of a standard CMOS inverter. Also, the level-shifting inverting circuit includes a switch circuit that includes a differential pair. The differential pair has the blanking logic signal at one input, and a bias signal at the other input. The switch circuit is coupled to a voltage divider that provides an output voltage that is pre-determined by a resistor ratio when the switch circuit is open. If the blanking logic signal is low, the switch circuit is open. Conversely, if the blanking logic signal is high, the switch circuit is closed, and sinks current from the voltage divider, causing the output voltage to correspond to a second pre-determined voltage level.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: October 7, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Hon Kin Chiu
  • Patent number: 7432696
    Abstract: A low-voltage current mirror circuit is provided. The low-voltage current mirror circuit includes a current mirror including first and second transistors, a buffer circuit, and a third transistor. The first transistor is the input transistor to the low-voltage current mirror circuit. Additionally, the source of the third transistor is coupled to the drain of the first transistor. The buffer circuit is configured to cause the voltage at the gate of the third transistor and the voltage at the gage of the first transistor to be substantially equal. Also, the low-voltage current mirror circuit is arranged such that the drain current provided to the third transistor is relatively small such that the Vgs of the third transistor is roughly equal to the threshold voltage VTH. Accordingly, the input voltage of the low-voltage current mirror circuit is approximately equal to Vgs-VTH.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: October 7, 2008
    Assignee: National Semiconductor Corporation
    Inventor: Frank John De Stasi
  • Patent number: 7430755
    Abstract: A system and method for providing persistence in a secure network access by using a client certificate sent by a client device to maintain the identity of a target. A security handshake is performed with a client device to establish a secure session. A target is determined. A client certificate is associated with the target. During subsequent secure sessions, the client certificate is used to maintain persistent communications between the client and a target. A session ID can be used in combination with the client certificate, by identifying the target based on the session ID or the client certificate, depending on which one is available in a client message.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: September 30, 2008
    Assignee: FS Networks, Inc.
    Inventors: John R. Hughes, Richard Roderick Masters, Robert George Gilde
  • Patent number: 7430133
    Abstract: A switched-capacitor type voltage regulator is provided. The regulator includes a flying capacitor and switches, including first and second transistors which operate as switches. The switches are arranged to operate such that the flying capacitor is coupled to an input voltage during a first phase, and switched to provide an output voltage during a second phase. During the first phase, the first transistor is employed to couple the capacitor to the input voltage, and a second transistor is employed to couple (the other side of) the capacitor to another node (e.g. Ground). Additionally, another switch is coupled between the gate and the drain of either the first transistor or the second transistor. Also, during the first phase, if the input voltage is greater than the output voltage, the other switch is closed so that the transistor that the other switch is connected to operates as a diode.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: September 30, 2008
    Assignee: National Semiconductor Corporation
    Inventors: William J. McIntyre, Mengzhe Ma
  • Patent number: 7427513
    Abstract: The present invention is based on the discovery that the methods described herein for the production of metallic colloids result in colloids exhibiting increased signal enhancement and reproducibility for the SERS detection of biomolecules. Thus, using the methods of the invention, a wide variety of biomolecules can be detected with a greater sensitivity and reliability.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: Tae-Woong Koo, Selena Chan, Xing Su, Jingwu Zhang, Lei Sun
  • Patent number: 7426037
    Abstract: Diffraction grating based fiber optic interferometric systems for use in optical coherence tomography, wherein sample and reference light beams are formed by a first beam splitter and the sample light beam received from a sample and a reference light beam are combined on a second beam splitter. In one embodiment, the first beam splitter is an approximately 50/50 beam splitter, and the second beam splitter is a non 50/50 beam splitter. More than half of the energy of the sample light beam is directed into the combined beam and less than half of the energy of the reference light beam are directed into the combined beam by the second beam splitter. In another embodiment, the first beam splitter is a non 50/50 beam splitter and the second beam splitter is an approximately 50/50 beam splitter. An optical circulator is provided to enable the sample light beam to bypass the first beam splitter after interaction with a sample.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: September 16, 2008
    Assignee: Boston Scientific Scimed, Inc.
    Inventors: Isaac Ostrovsky, Mark D. Modell, Robert J. Crowley
  • Patent number: 7426315
    Abstract: A method for removing blocking artifacts from moving and still pictures, comprising classifying horizontal and vertical boundaries in each picture as blocky or non-blocky; for each blocky boundary, defining an adaptive, picture content-dependent, one-dimensional filtered pixels region of interest (ROI) that crosses the boundary and is bound at each of its ends by a bounding pixel; defining a finite filter having a length correlated with the length of the ROI; defining a filtering pixels expansion that uniquely determines the padding values of the finite length filtered pixels ROI for the finite length filtering; and filtering the ROI pixels using the finite filter and the filtering expansion.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: September 16, 2008
    Assignee: Zoran Microelectronics Ltd.
    Inventors: Eyal Frishman, Tamir Sagi, Noam Oren
  • Patent number: 7423801
    Abstract: Apparatus for enhancing vision of a user includes a focal modulation device (22), which is adapted to focus light from objects in a field of view of the user onto the retina while alternating between at least first and second focal states that are characterized by different, respective first and second focal depths, at a rate in excess of a flicker-fusion frequency of the user.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: September 9, 2008
    Assignee: Invisia Ltd
    Inventors: Micha Kaufman, Kalman Kaufman
  • Patent number: 7421795
    Abstract: A metrology system comprises a support structure, a fixture having a bottom surface resting on a surface of the support structure and moveable relative to the support structure, and a first measurement assembly for interacting with a workpiece held by the fixture to measure a characteristic of the workpiece. One of the bottom surface of the fixture and the surface of the support structure comprises sapphire, and the other of the bottom surface of the fixture and the surface of the support structure comprises a metal.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: September 9, 2008
    Assignee: Seagate Technology LLC
    Inventors: Ananda V. Mysore, Steve G. Gonzalez