Abstract: According to one embodiment, a virtual channel synchronous dynamic random access memory (VCSDRAM) (100) can perform a high-frequency test with lower frequency test equipment. The VCSDRAM (100) can include a command decoder circuit (102) that can receive a transfer command and provide a transfer command signal (124). A transfer operation start signal generating circuit (106) can receive and latch the transfer command signal (124). The command decoder circuit (102) can then receive an active command and provide an active command signal (120). The active command signal (120) can result in the generation of a main storage activating signal (128). Having latched the transfer command signal (124), the transfer operation start signal generating circuit (106) can generate a transfer operation start signal (130) in response to the active command signal (120). The transfer operation start signal (130) can generate a control signal (132).

Abstract: A semiconductor memory device, such as a SDRAM operating in a multi-bit prefetch mode, having reduced on chip noise associated with the switching of signal lines is disclosed. According to one embodiment, the semiconductor memory device may include first and second memory cell segments (201 and 202). A first Y-address buffer decoder 100-1 can be connected to the first memory cell segment 201 and a second Y-address buffer decoder 100-2 can be connected to the second memory cell segment 202. The first Y-address decoder 100-1 receives a Y-address and a first latch signal CLK1. The second Y-address decoder 100-2 receives a Y-address and a second latch signal CLK2. A clock generating circuit 400 receives an external clock signal CLK and synchronously generates the first and second latch signals (CLK1 and CLK2).

Abstract: According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG1 between a first input SA1 and a first latch node N1, and a second transfer gate TG2 between a second input SA2 and a second latch node N2. A first transfer gate may include complementary transistors NM1 and PM1. Transistor NM1 can receive a control signal /SE at a control gate while transistor PM1 can receive a complementary control signal SE at a control gate. Transistor NM1 may include a parasitic capacitance C0N and transistor PM1 may include a parasitic capacitance C0P that is essentially equivalent to C0N. In such an arrangement, noise at first input SA1 generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

Abstract: According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG1 between a first input SA1 and a first latch node N1, and a second transfer gate TG2 between a second input SA2 and a second latch node N2. A first transfer gate may include complementary transistors NM1 and PM1. Transistor NM1 can receive a control signal /SE at a control gate while transistor PM1 can receive a complementary control signal SE at a control gate. Transistor NM1 may include a parasitic capacitance CON and transistor PM1 may include a parasitic capacitance COP that is essentially equivalent to CON. In such an arrangement, noise at first input SA1 generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

Abstract: A method and apparatus for data transmission and reception is disclosed. A data transmission/reception apparatus (300) may allow data to be transferred between a data bus (IOT and ION) and a bit line pair (Di and DBi). The data transmission/reception apparatus (300) may include a column select transfer gate circuit (12) that may receive column select signals (YU and YLi) from a column address decode circuit (14). Column select transfer circuit (12) may include a transfer gate circuit (12i) that may provide a data transmission/reception path between a data bus (IOT and ION) and a bit line pair (Di and DBi). Transfer gate circuit (12i) may include connection nodes that may have parasitic capacitors (Ci and CBi). A precharge circuit (16) may allow previous data signals stored on parasitic capacitors (Ci and CBi) to be removed during a precharge operation before a subsequent data transfer operation is executed.

Abstract: A semiconductor integrated circuit including a logic circuit having an insulated gate field effect transistor (IGFET) (352) with a reduced threshold voltage that may compensate for a reduced voltage supply is provided. The IGFET may receive a signal line (340) at a gate terminal and may provide a controllable impedance path between a signal line (320) and a node (ND). The logic circuit may include a stand-by mode in which the IGFET (352) may receive a potential at a source electrode that may be approximately equal to the potential at a drain electrode. In this way, leakage current may be reduced.

Abstract: A semiconductor memory device having serial access read mode including a latency period and a serial access period is provided. Semiconductor memory device (100) can include sense amplifier (110), a reference voltage generator (200), and a period detection circuit (101). Period detection circuit (101) can provide a control signal (RCL) indicating the latency period or the serial access period. Reference voltage generator (200) can provide a reference voltage (REF) having a first potential during the latency period and a second potential during the serial access period. In this manner, it may be possible to increase the speed of reading memory cell data by reducing the timing differences between reading a memory cell having a first data state and a memory cell having a second data state.

Abstract: A semiconductor memory device (10) having a peripheral ground line (GND) receiving charge when discharging a sub-word line (SWL) is provided. The semiconductor memory device (10) can include a row decoder (XDEC1), RA driver (RAD11), and sub-decoder blocks (SB). Row decoder (XDEC1) may activate a main word line (MWL) based on a received address value. RA driver (RAD11) may activate a sub-decoder block (SB) from a group of sub-decoder blocks coupled to the activated main word line (MWL). RA driver (RAD11) may provide a current path (4) to peripheral ground (GND) when the sub-word line (SWL) transitions from the activated state to the unactivated state. Non-selected sub-word lines may have a current path (1, 2, or 3) to a word line ground (GNDXDEC) for holding the other word lines at a “quiet” ground potential. Noise produced from discharging a sub-word line may not affect non-selected word lines.

Abstract: A logic circuit (200) having a critical path input signal (C2) that can have a reduced input capacitance and a logic output (D2) that can have a reduced voltage swing is disclosed. According to one embodiment, the logic circuit may include an input circuit (210), a driver circuit (220), and a load circuit (230). Driver circuit (220) can include stacked transistors (N4 and N5) of the same conductivity type, which can generate a logic output (D2) that can have a reduced voltage swing. Driver circuit (220) can generate a feedback signal that can control the impedance of a load circuit (230). Load circuit (230) can be actively controlled to improve the response of a logic evaluation node (V2).

Abstract: Register and latch circuits are disclosed that can have faster operating speeds. According to one embodiment, a register circuit (100) may include a master latch circuit (102) and a slave latch circuit (104). The slave latch circuit (104) may include an n-channel transistor M13 between an input of the slave latch circuit (104) and the gate of a p-channel driver transistor M11. A p-channel transistor M14 can be provided between the input of the slave latch circuit (104) and the gate of an n-channel driver transistor M12. The driver transistors M11 and M12 can be driven by way of the source-drain paths of transistors M13 and M14, respectively.

Abstract: A method of manufacturing a semiconductor memory cell is provided. The semiconductor memory cell can include a memory cell transistor (10) and a capacitor. The capacitor can be formed in a groove (13) formed in an interlayer insulation film (12). The capacitor can have a lower electrode including a selective growth film (18) which may be selectively deposited on a lower electrode film (16). Selective growth film (18) can be a ruthenium film having a thickness of approximately 5˜10 nm and may serve as a buffer which may prevent lower electrode and a capacitor insulation film (20) from deterioration in integrity which could cause increased leakage currents.

Abstract: A semiconductor memory (200) having a plurality of banks (10 and 20) of memory cells in which a parallel test operation can allow bits from each bank to be tested in parallel. According to one embodiment, the semiconductor memory may include a data amplifier (30) having a selection circuit (110), data sense circuit (120), data output circuit (130), control circuit (140), and comparator (C1). In a normal mode of operation, the selection circuit (110) may be coupled to receive I/O busses (IOAT/N and IOBT/N) from memory banks (10 and 20) and based on selection control signals (TR1 to TR4), may select data to be amplified by data sense circuit (120) and output to a read/write bus RWBST/N. In a test mode of operation, the selection circuit (110) may be coupled to receive I/O busses (IOAT/N and IOBT/N) from memory banks (10 and 20) and may couple data from each memory bank (10 and 20) to a data sense circuit (120) to be amplified and applied to comparator (C1).

Abstract: A method of manufacturing a semiconductor device that can limit etch damage is disclosed. According to one embodiment, isolation regions (102) may be formed in a substrate (101). A word line (103) may be formed in a first region. A protective film (105) may be formed over the first region and a second region. A protective film (105) may then be etched from the second region but retained in the first region. A sidewall layer (107) may then be formed over the first and second regions, and etched to form sidewalls (107-a). The protective film (105-a) over the first region can reduce etch damage. Further, because a protective film (105-a) can be thinner than a sidewall layer (107), a resulting step height between the first region and second region may be reduced. Reductions in such a step height can result in better focus margins for subsequent photolithographic steps.

Abstract: A semiconductor storage device (100) is disclosed that includes sense amplifier rows (SA0 to SA16) that receive a common sense amplifier drive voltage VINTA supplied by a internal voltage driver (5) having a high current source mode. According to one embodiment, the semiconductor storage device (100) may include banks of memory cells (B0 to B15), row decoders (DC0 to DC15), bank enable generation circuits (EC0 to EC15), sense amplifier rows (SA0 to SA16), sense amplifier drivers (DRA0 to DRA16), sense amplifier control circuits (SCA0 to SCA16), and internal voltage drivers (5 and 6). Internal voltage driver (5) can include a high current source or high voltage source mode, which can be received by a sense amplifier row (SA0 to SA16) during predetermined initial sense period. Other sense amplifier rows (SA0 to SA16) having already sensed data can be isolated from internal voltage driver (5) during the high current source or high voltage source mode.

Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. In a first embodiment, the DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) is formed within a silicon mesa (310), and includes a source region (316), drain region (318) and channel region (320). The channel region (320) is formed below a furrow (322) that is inset with respect to the top surface of the silicon mesa (310). The channel region (320) has a smaller thickness than that of the source region (316) and drain region (318). A top gate (314) is disposed over the channel region (320). Due to the reduced thickness channel region (320), greater control of the operation of the pass transistor (302) is provided, including an off state with reduced source-to-drain leakage. The greater thickness of the source region (316) and drain region (318) (relative to the channel region (320)) provides greater immunity to the adverse effects of contact spiking.

Abstract: According to disclosed embodiments, a semiconductor memory is disclosed that includes a memory array connected to a number of registers by a transfer bus of reduced size. Reduction of transfer bus size can be achieved without a significant increase in data processing speed. According to one embodiment (300) a semiconductor memory can include a number of cell regions (302-0 and 302-1) arranged in a first direction. Sense amplifier banks (304-0 to 304-2) are connected to the cell regions (302-0 and 302-1) and a transfer bus (310-0/1) is disposed over the cell regions (302-0 and 302-1) in the first direction. The transfer bus (310-0/1) includes switching circuits (312-0 and 312-1) corresponding to each cell region (302-0 and 302-1). The switching circuits (312-0 and 312-1) can divide the transfer bus (310-0/1) into a number of transfer bus line portions (314-0/1, 316-0/1 and 318-0/1).

Abstract: A semiconductor device, such as a SDRAM, having internal signals (FICLK and ICLK) generated with similar timings with respect to each other, even when operating at a frequency that is too low for proper operation of a synchronous circuit (103). According to one embodiment, the semiconductor device may include an internal signal generator (100) having a first stage circuit (101), timing control circuit (110) and synchronous circuit (103). The first stage circuit (101) may receive an external CLK and generate an internal signal ICLK′. The timing control circuit (110) may be coupled to receive internal signal ICLK′ and generate internal signal ICLK′. The synchronous circuit (103) may be coupled to receive internal signal ICLK′ and generate internal signal FICLK. Internal signals (FICLK and ICLK) may have a timing with respect to one another in a normal mode of operation.

Abstract: A semiconductor storage device that can be selectable between input/output (I/O) configuration and have reduced area for data buses and/or reduced number of circuit elements is disclosed. According to one embodiment, a semiconductor storage device may include first and second memory cell arrays (10 and 12). Eighteen first sense amplifiers (SA(L)1-18) can be connected to the first memory cell array (10) and eighteen second sense amplifiers (SA(R)1-18) can be connected to the second memory cell array (12). In addition, eighteen first I/O circuits (I/O(L)1-18) may correspond to the first sense amplifiers (SA(L)1-18) and eighteen second I/O circuits (I/O(R)1-18) may correspond to the second amplifiers (SA(R)1-18). Eighteen data buses (DB1-DB18) can be situated between the sense amplifiers (SA(L)1-18 and SA(R)1-18) and I/O circuits (I/O(L)1-18 and I/OR)1-18). Each data bus may be separated into at least two different portions by a disconnecting device (T1-T18). In one I/O configuration (e.g.

Abstract: According to one embodiment, an asynchronous static random access memory (SRAM) circuit (100) can provide reduced power consumption and high-speed access. An SRAM circuit (100) may include address registers (122 and 128) that can store a write address from one write operation and output the stored write address during a subsequent write operation. A data register (138) may also be included that can store write data from one write operation and output the stored write data during a subsequent write operation. Memory cells of a memory cell array (102) may be selected according to a pulse word signal PW. A pulse word signal PW can be generated in response to transitions in an address and transitions in a write enable signal /WE. Hit address comparators (220) within address registers (122 and 128) in combination with a hit AND gate (136) can activate a HIT ALL signal when a stored write address matches an applied read address.

Abstract: A method of manufacturing a semiconductor device having transistors with lightly doped diffusion regions (LDD) and self-aligned contacts to a reduced inter-gate spaces is disclosed. According to one embodiment, a method may include forming a gate and top insulating layer (004 and 005) on a semiconductor substrate (001). LDD regions (007) may be formed in a first area (Rpc) and source/drain regions (011) may be formed in a second area (Rmc). An etch stop layer (012), which may comprise silicon nitride, can then be formed. Sidewalls (006), which may comprise silicon dioxide, may be formed on gate layer (004) in a first area (Rpc), while inter-gate spaces in the second area (Rmc) may be filled with a sidewall layer. Source/drain regions (008) may then be formed in a first area (Rpc). A heat treatment can be applied that can restore etch resistance properties of the etch stop layer (012) which can be degraded when source/drain regions (008) are formed.