Abstract: Nonvolatile memory elements are disclosed which can have increased capacity, reduced operating voltage and/or faster operating speeds. According to one embodiment, a nonvolatile memory element can include a first diffusion layer (2) and a second diffusion layer (3) formed in a main surface of a substrate (1). A laminate film can be formed near a first diffusion layer (2) and/or a second diffusion layers (3) that includes a first insulating film (4a or 4), a second insulating film (5a or 5), and a third insulating film (6a or 6). A gate insulating film (7) can be formed a channel region and gate electrode (8) can be formed to cover gate insulating film (7) and the laminate film(s) that has a T-shape. A gate electrode (8) can have end portions that sandwich a first insulating film (4a or 4), a second insulating film (5a or 5), and a third insulating film (6a or 6) with a first diffusion layer (2) and/or second diffusion layer (3).

Abstract: A clock generating circuit (100) that may prevent an erroneous clock signal from being provided to an internal logic circuit (105) has been disclosed. A clock generating circuit (100) may include a variable voltage generating circuit (101), an oscillating circuit (103), and a control circuit (104). Oscillating circuit (103) may provide an original clock signal (157). A charging circuit (122, 123, and 124) may provide charging of a signal (159) when an original clock signal (157) achieves a predetermined amplitude. When signal (157) charges sufficiently, an oscillation stabilization signal may be provided to enable the generation of a synthesized clock signal (160). Also, at this time, a reduced voltage (170) may be provided to power an oscillating circuit (103). In this way, current consumption may be reduced and failures due to providing an erroneous clock signal to an internal logic circuit may be reduced.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A frequency synthesizer (100) that may have reduced spurious noise caused by a voltage controlled oscillator (VCO) (4) output sneaking into an input side of a phase comparison circuit (1) has been disclosed. A beat frequency component that may be generated by mixing of a portion of a VCO output sneaking into an input side of a phase comparison circuit (1) through a reference signal (REF) or a comparison signal (SIG) may be shifted to a high frequency region by providing a modulator circuit (7) on a reference signal side or a comparison signal side. Thus, a low pass filter circuit (3) may provide attenuation to the spurious noise. In this way, spurious noise in the VCO output may be reduced.

Abstract: A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate oxide film (30). The active gate film (2) may be located in a central portion under of a gate electrode (3). The gate oxide film (30) may be located under end portions of the gate electrode (3). In this way, a distance between a shoulder portion of a trench (11) and a gate electrode (3) may be increased. Thus, an electric field concentration in the shoulder portion of the trench (11) may be decreased and memory cell characteristics may be improved.

Abstract: A variable gain amplifier circuit (100) that may have a gain exponentially changed has been disclosed. A variable gain amplifier circuit (100) may include a first OTA (Operational Transconductance Amplifier) (11) and a second OTA (12). A first OTA (11) may receive a differential voltage at input terminals (IN1 and IN2). A second OTA (12) may receive an output from a first OTA (11) and may provide a differential output voltage at output terminals (OUT1 and OUT2). A second OTA (12) may have second OTA input terminals and second OTA output terminals commonly connected to output terminals (OUT1 and OUT2). A small-signal transconductance of the first and second OTAs (11 and 12) may be proportional to driving currents. A first OTA (11) may have a driving current of I0{1+tan h(x/a)} and a second OTA (12) may have a driving current of I0{1?tan h(x/a)}, where ?1<x<1 and a is a constant.

Abstract: A semiconductor apparatus including programmability that may allow a SSTL interface or LVTTL interface is provided. A reference configuration circuit (100) may provide a primary reference potential VREF0 and secondary reference potential VREF. Reference configuration circuit (100) may include a bond pad (PAD1), a reference potential generation circuit (1), a control circuit (50), a reference selection circuit (60), and a secondary reference potential generation circuit (70). During a wafer test mode, primary reference potential VREF0 and secondary reference potential VREF may be provided from a potential that may be applied to bond pad (PAD1).

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A semiconductor device and method of manufacture are provided wherein a contact hole can be formed with increased contact area while maintaining sufficient isolation between an electroconductive layer deposited in the contact hole and an adjacent wire. According to one embodiment (100), a double-layered side-wall insulating layer can be formed within a contact hole (116). The upper (second) side-wall insulating layer (120) can be etched back to expose part of the lower (first) side-wall insulating layer (118) formed in the bottom of the contact hole (116). Subsequently, the exposed portion of the first side-wall insulating layer (118) can be subject to a wet etch to remove the portion of the first side-wall insulating layer (118) at the bottom of the contact hole (116).

Abstract: A phase comparison circuit for generating control voltages for a number of varactors of a phase locked loop (PLL) circuit has been disclosed. According to a particular embodiment, a number of phase difference detection circuits (101, 102 and 103) can be successively activated in response to a set of activation signals to generate output voltage signals (Vtunei). Output voltage signals (Vtunei) can vary according to an elapsed period time, and thus represent a phase difference. Each phase difference detection circuit (101, 102 and 103) can activate a trigger signal (Trg) when an internal voltage signal equals a predetermined value. A main signal (SIG) can be input as an activation signal to a first stage phase difference detection circuit (101). A trigger signal from a first stage phase difference detection circuit (101) can be input as an activation signal to a subsequent stage phase difference detection circuit (102).

Abstract: An output buffer circuit is disclosed that can enhance AC performance and suppress reflected noise. An output buffer circuit can include a first driver circuit (21) and at least one second driver circuit (2n) for sending signals on a transmission line. A first driver circuit (21) can have an output impedance that essentially matches a characteristic impedance of the transmission line. A signal judging circuit (1) can determine when an input data signal (DATA) makes a transition. During such transition times, a signal may be driven on the transmission line by both the first and second driver circuits (21 to 2n) according to the input data signal. When the input signal data has the same value for a predetermined amount of time, a signal may be driven on the transmission line by the first driver circuit (21), and not the second driver circuit (2n) according to the input data signal. Transitions in an input data signal may be represented by data signals of a signal judging circuit (1) having different values.

Abstract: A phase comparator is disclosed that can provide a phase comparison result at high speed that essentially does not vary according a power source voltage, ambient temperature and/or manufacturing process conditions, or the like. A phase comparator (10) may include one-shot pulse generating units (14 and 24) that output one-shot pulses according to input data signal DAT and clock signal CLK, respectively. An R-S flip-flop (16) can receive one-shot pulses from one-shot pulse generating units (14 and 24) at set and reset inputs, respectively. An output flip-flop (17) can select between an output signal of R-S flip-flop (16) and a delay signal “a8” generated from input data signal DAT, and latch such a result according to a delayed clocks signal CLK.

Abstract: A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

Abstract: A voltage amplifying circuit (100) that may have a selectable gain has been disclosed. Voltage amplifying circuit (100) may include a voltage amplifier (2) and a gain changing unit (7). A gain changing unit (2) may be capable of changing at least one of: a capacitance between a signal input terminal (6) and an input terminal of a voltage amplifier, the capacitance between an input terminal of a voltage amplifier and a ground (or reference potential), and a capacitance between an input and an output terminal (3) of a voltage amplifier. In this way, a gain from a signal input terminal (6) to an output terminal (3) of a voltage amplifier of a voltage amplifying circuit (100) may be changed.

Abstract: A charge pump current compensating circuit (4) including feedback so that a difference between a charging current and a discharging current may be reduced is disclosed. Charge pump current compensating circuit (4) may include a current source leg (I11, N16, and N15), a first current mirror leg (P13, P14, N14, and N13), a second current mirror leg (P11, P12, N12, and N11), and a compensation circuit (5). Compensation circuit (5) may provide compensation to control insulated gate field effect transistors (IGFETs) (P12 and P13) so that a charging current and a discharging current may be essentially the same even when output impedances of IGFETs (P12 and N12) are different.

Abstract: A semiconductor apparatus and method for making the semiconductor apparatus are provided. The semiconductor memory device can include functional circuit blocks (100) having a multi-layer wiring structure for providing electrical connections between device elements within functional circuit blocks (100). Multi-layer wiring structure can include a wiring layer (M2) disposed in a M2 wiring layer horizontal track (120) and a M2 wiring layer vertical track (122). M2 wiring layer horizontal track (120) provides electrical connections by using wiring layer (M2) disposed in a horizontal direction and M2 wiring layer vertical track (122) provides electrical connections by using wiring layer (M2) disposed in a vertical direction. A wiring layer (M1) can form electrodes having electrical connections to diffusion regions of the device elements in functional circuit blocks (100). Wiring layer (M1) can have a higher sheet resistance and higher melting point than wiring layer (M2).

Abstract: A voltage step-down circuit (100) that may provide an internal voltage (VINT) by reducing an external power source (VDD) has been disclosed. A voltage step-down circuit (100) may include a voltage step-down portion (10) and a compensation current source portion (20). Voltage step-down portion (10) may compare a reference voltage (VREF) with an internal voltage (VINT) and control an output current (I0) accordingly. An internal circuit (1) connected to receive internal voltage (VINT) may transition from a standby state to an active state in accordance with an activation signal. Compensation current source portion (20) may provide a compensation current (Ic) when internal circuit (1) is in a standby state. In this way, voltage step-down portion (10) may be biased to provide sufficient output current (I0) so that a response time may be improved and variations in internal voltage (VINT) may be reduced.

Abstract: A circuit is disclosed that can output signals from different circuit blocks at a common output terminal with a smaller number of transistors than conventional approaches. When a level shifter circuit receives a high voltage level at a control terminal (2), a level shifter unit (12) is placed in the operational state to provide an output signal from a low voltage system block, and a clocked inverter (106) is placed in the non-operational state. When a level shifter circuit receives a low voltage level at a control terminal (2), a clocked inverter (106) is placed in the operational state to provide an output signal from a high voltage system block. At the same time, PMOS transistor (105) can be turned on, resulting in PMOS transistors (5) being turned off. Further, NMOS transistors (109 and 110) are turned off. This can result in an output impedance of a level shifter unit (12) being set to a high impedance state.

Abstract: A semiconductor integrated circuit device is disclosed that can provide greater flexibility of layout while essentially ensuring circuit characteristics, and at the same time providing an minimum electrostatic discharge breakdown withstand value according to Charged Device Model (CDM) at all input/output (I/O) terminals. For each I/O terminal a size of a CDM protective device can be optimized in response to reference electric potential wiring resistance between an input protective device, a MOSFETs that can constitute an internal circuit, and an input resistance.