Abstract: A semiconductor storage device is disclosed that can lower sense amplifier input potentials to about a half supply potential (VCC/2) to speed up sense amplifier operations. According to one embodiment, a semiconductor storage device (100) may include a pair of digit lines (104 and 106), a memory cell (108) that can place stored data on digit lines (104 and 106), a sense amplifier (112) that may read memory cell data on digit lines (104 and 106), and switching devices (120-a and 120-b) connected between sense amplifier inputs (112-a and 112-b) and digit lines (104 and 106). Digit lines (104 and 106) may be precharged to a high potential. Memory cell data may then be placed on the digit lines (104 and 106). Prior to the activation of the sense amplifier (112) switching devices (120-a and 120-b) may lower the digit line potentials to a level more conducive to sensing by the sense amplifier (112). In this way, a read operation by the sense amplifier (112) may be faster than conventional approaches.

Abstract: According to one embodiment (100), high speed, reduced power logic circuits (114-1 to 114-16) can have load impedances that are changed synchronously with input signals. A load impedance control circuit (104) can provide a load impedance control signal LC synchronously with a clock signal CLK. The amplitude of the load impedance control signal LC can be less than a power supply voltage VCC. The load impedance control signal LC can be supplied to the gate of a PMOS load transistor (116) in a logic circuit (114-1). When NMOS logic transistors (118 and 120) are turned on, PMOS load transistor (116) can have a high impedance due to the load impedance control signal LC. In this way, the potential at the input of inverter (122) can be rapidly changed to quickly obtain a decoder output value X0.

Abstract: According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG1 between a first input SA1 and a first latch node N1, and a second transfer gate TG2 between a second input SA2 and a second latch node N2. A first transfer gate may include complementary transistors NM1 and PM1. Transistor NM1 can receive a control signal /SE at a control gate while transistor PM1 can receive a complementary control signal SE at a control gate. Transistor NM1 may include a parasitic capacitance C0N and transistor PM1 may include a parasitic capacitance C0P that is essentially equivalent to C0N. In such an arrangement, noise at first input SA1 generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

Abstract: A semiconductor storage device may shorten burn-in test times without adversely affecting a normal mode of operation. According to one embodiment, a determination circuit 60 can select multiple memory section (10 and 20) simultaneously in a burn-in test, and prevent such a simultaneous selection of multiple memory sections (10 and 20) in a normal mode of operation.

Abstract: According to one embodiment, a semiconductor memory device can generate a decoder enable signal (YREDB) that can enable and disable a decoder circuit according to external address signals such that the decoder circuit is enabled when ordinary memory cells are accessed and disabled when redundant memory cells are accessed. The semiconductor memory device may include redundancy circuits (010) that may be placed in a first state when an ordinary memory cell is accessed and in a second state when a redundant memory cell is accessed. A combining circuit can activate the decoder enable signal (YREDB) when the redundancy circuits (010) are in the first state and deactivate the decoder enable signal (YREDB) when the redundancy circuits (010) are in the second state. In addition, a pulse generator (011) can provide an ordinary mode pulse (YRDB) in synchronism with all external clock.

Abstract: According to one embodiment, a multistage readout circuit may include a smaller circuit size and/or faster circuit response. A memory cell (002) may have more than two states (VT0-VT3). Determination of a particular state can involve various stage results generated by activating a word line at different levels. A sense amplifier (003) can provide an output value at each stage. In one arrangement, a second stage value can determine if a memory cell (002) has two of four states and can be latched in a first latch circuit (041). Such a second stage value can then determine if a first stage value or third stage value is latched in a second latch circuit (042). A first/third value can determine if a memory cell (002) has one of the two states initially determined by the second stage value.

Abstract: A static random access memory (SRAM) circuit includes four-transistor memory cells and is capable of high-speed reliable read operations. According to one embodiment, a SRAM circuit includes “n” memory cells (200-1 to 200-n) connected to digit line pairs (202-0 and 202-1). When selected, a memory cell (200-1 to 200-n) can draw an on current (Ion). When deselected, a memory cell (200-1 to 200-n) can draw a leakage current (Ioff) that can maintain a data value stored in a memory cell. High-speed and reliable operations may be achieved by meeting the following relationship: Ion>K*(n−1)*Ioff, where K is 1 or more.

Abstract: According to one embodiment, a master-slave flip-flip circuit (MS-FF) (100) includes master input transfer gate (108) connected to the input of a master latch portion (102) and a slave input transfer gate (110) connected to the input of a slave latch portion (104). A clock generating circuit (112) includes a first inverter (114-0) that provides an inverted clock signal CB1 and a second inverter (114-1) that provides a non-inverted clock signal C1. The clock signals C1 and CB1 are provided to the slave input transfer gate (104). The clock signals C1 and CB1 are further provided to the master input transfer gate (108) through clock lines (116-0) and (116-1) which have a parasitic resistances R1 and R2. The parasitic resistances R1 and R2 delay the C1 and CB1 signals and thereby provides a delayed inverted clock signal CB2 and a delayed non-inverted clock signal C2 to the master input transfer gate (108).

Abstract: A semiconductor memory device can inhibit undesirable fluctuations of memory cell signals that can occur at remote ends of the device, thereby improving sense margins over conventional approaches. The semiconductor memory device (100) can include a half power source (HVCC) level generating circuit that supplies a half-supply potential for an opposite-to-cell level and for precharging digit lines. Shunting circuits (103) can shunt the connection between the opposite-to-supply level HVCP1 and the precharge (reference) level, and are situated at various places close to sense amplifier areas. This arrangement can make it possible to inhibit fluctuations in signal levels that can occur due to capacitive coupling of indeterminate data nodes when a refresh operation is introduced after power-up. Such inhibiting of fluctuations can occur even for memory cells that are situated remotely from the HVCC level generating circuit. Consequently, sense margins can be improved over conventional approaches.

Abstract: A nonvolatile semiconductor storage device is disclosed that can have memory cells with a narrower erase threshold voltage distribution, a low power supply voltage, and high access speeds. According to one embodiment, a nonvolatile semiconductor device (100) may include a detect mode that can determine if a selected memory cell (102-01 to 102-32) has an erase threshold voltage below a predetermined value. In a detect mode, a cell check signal CELLCHK is active, resulting in a cell check voltage generator circuit (128) generating a detect bias voltage. According to power switch control signals PSCTRL, a power source switch 124 connects the sources and well(s) of the memory cells (102-01 to 102-32) to the cell check voltage generator circuit (128). Word lines (104-0 to 104-n) of deselected memory cells are driven to a low power supply voltage. The word line deselect bias voltage and detect bias voltage can prevent low erase threshold voltage memory cells from generating leakage current on a bit line.

Abstract: A double-data rate (DDR) memory device is disclosed that can be configured for testing on an ordinary memory tester. The DDR memory may include a DDR input circuit (102), a single data rate input circuit (104), a word line control circuit (106), a bit line control circuit (108), and a memory cell array (110). Normal write operations may be performed by selecting the DDR input circuit (102). Test write operations may be performed by selecting the SDR input circuit (104). Such an arrangement can enable a DDR memory device to be tested in an ordinary SDR memory tester.

Abstract: A semiconductor memory (100) is disclosed that includes a memory cell array (102) coupled to a register array section (104) that can function as a cache. Access times for misses to the register array section (104) during a continuous read operation can be reduced. A memory cell array (102) is coupled to the register array section (104) by a first transfer bus (TBT1-1 to TBN1-i). First transfer bus (TBT1-1 to TBN1-i) is connected to a local read/write bus (LRWBT and LRWBN) by transistors (106-1 to 108-i) and to register arrays (116-1 to 116-(i+j)) by first switches (118-1 to 118-(i+j)). In a continuous read operation, during a register array section miss, transistors (106-1 to 108-i) are turned on and the first switches (118-1 to 118-(i+j)) are turned on.

Abstract: According to one embodiment, a semiconductor memory (100) can include a firststage control circuit (106) that generates a first stage control signal &phgr;0, a data input/output (DQ) control circuit (116) that generates a DQ control signal &phgr;1 based on the first stage control signal &phgr;0 and a row address enable signal RASE, and a data mask (DQM) control circuit (114) that generates a DQM control signal &phgr;2 based on the first stage control signal &phgr;0, row address enable signal RASE, and a column address strobe (CAS) latency equal to one value (CLT1). A DQ first-stage circuit (112) is coupled to the DQ control circuit (116) and a DQM first-stage circuit (110) is coupled to the DQM control circuit (116). The DQ and DQM first-stage circuits (110 and 112) can be deactivated when the RASE signal, CASE signals are inactive and the CAS latency is greater than one.

Abstract: According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK′ in a test mode. The ICLK′ signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK′ signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).

Abstract: According to disclosed embodiments, a semiconductor memory (100) can include a restore voltage control circuit (106) that can supply a first internal voltage V.sub.INT that is lower than an external power supply voltage Vcc, a second internal voltage V.sub.INTS 1 that is lower than the first internal voltage V.sub.INT, and a third internal voltage V.sub.INT 2 equal to or less than the first internal voltage V.sub.INT and greater than the second internal voltage V.sub.INTS 1. The semiconductor memory (100) can further include a p-channel MOS transistor (T108) that can provide a conductive path between a voltage supply path (116) and a sense amplifier (104) in response to a sense signal Se at the first internal voltage V.sub.INT. A switch signal generating circuit (112) can supply a switch signal Sw that can change the potential on the voltage supply path (116) from the second internal voltage V.sub.INTS 1 to the third internal voltage V.sub.INTS 2 while transistor T108 is conductive.

Abstract: According to one embodiment, a semiconductor storage device (100) can provide an enhanced rate of defective sub-word line replacement by independently controlling the activation and deactivation of redundancy sub-word lines (Sw(1,0 to Sw(5,2))). Redundancy sub-word lines (Sw(1,0 to Sw(5,2))) can be connected to different redundancy sub-word drivers (114a to 114e). Sub-word selecting circuits (126-1 to 126-4) can generate 2-bit redundancy sub-word selecting signals S11 to S14 from sub-word selecting signals XN and XT and fuse output signals H11-H14 received from a fuse circuit 124. Redundancy sub-word selecting signals S11 to S14 can independently activate and deactivate redundancy sub-word lines (Sw(1,0 to Sw(5,2))) coupled to redundancy sub-word drivers (114a to 114e).

Abstract: According to one embodiment (100), a synchronous semiconductor memory may include a first initial circuit (102), second initial circuit (104) and third initial circuit (106). The first initial circuit (102) can receive an external clock signal CLK and compare the external clock signal CLK to a reference voltage VREF. The comparison result can be amplified and output as a signal .phi.1. The second initial circuit (104) can receive a clock control signal CKE and compare the clock control signal CKE to a reference voltage VREF. The comparison result can be amplified and output as a signal .phi.2. The third initial circuit (106) can receive the external clock signal CLK, and is activated by a control signal .phi.7 that can correspond to the clock enable signal CKE. The third initial circuit (106) can compare the external clock signal CLK to a reference voltage VREF, and amplify and output the comparison result .phi.8. The embodiment (100) can further include a first control circuit (108) that can receive the .

Abstract: According to one embodiment, a semiconductor memory device can include a synchronous dynamic random access memory array and a register array formed from static random access memory cells. The memory device can be used in image processing, and reduce the time for data reads and writes during image reset operations. One embodiment (100) can include a memory cell array (102) having a number of memory cells arranged in rows and columns, and a register array (104) that includes a number of channel registers (106-11 to 106-mn) arranged rows and columns that correspond to at least a portion of the memory cell array rows and columns. The memory cells of a first column and the registers of a corresponding column are connected to one another by data transfer buses (108-1T/108-1N to 108-mT/108-mN). Data values can be written to memory cells and corresponding channel registers (106-11 to 106-mn) at the same time.

Abstract: An approach to rapidly pre-charging bit lines (104a and 104b) after a write operation to a memory cell (128) is disclosed. Following a write operation, a Y-select signal (Yj) and its inverse (/Yj) are maintained in an active state for a given period of time, keeping the transistors within a column selecting circuit (102) turned on. Pre-charging circuits (106 and 108) are also turned on. Consequently, the bit lines (104a and 104b) are pre-charged by the bit line pre-charging circuit (106), and by the pre-charging circuit (108) by way of a read bus (124) and the column selecting circuit (102). Furthermore, a write amplifier (112) is also activated, resulting in the bit lines (104a and 104b) being further pre-charged by way of a write bus (126) and the column selecting circuit (102).

Abstract: According to one embodiment, a word line control circuit (100) includes certain sub-array word lines (SWL-00 to SWL-03) coupled to one bank (BANK0)of memory cells and other sub-array word lines (SWL-10 to SWL-13) coupled to another bank (BANK1) of memory cells. Complementary main word lines (MWL and /MWL) are provided that can select groups of sub-array word lines in both banks when activated. Latch circuits (104-A0 to 104-B1) are provided for latching main word lines values. Such an arrangement allows a complementary main word line values to be latched for a first bank (BANK0), thereby selecting a group of sub-array word lines (SWL-00 to SWL-03) in the first bank (BANK0). The complementary main word line (MWL and /MWL) can then be activated again. The second complementary main word line values can then latched for a second bank (BANK1), thereby selecting a group of sub-array word lines (SWL-10 to SWL-13) in the second bank (BANK0).