Abstract: A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.

Abstract: A method of isolating a CMOS device on a silicon on insulator substrate, wherein the substrate includes an insulating layer of top silicon formed thereon, includes growing a gate oxide layer on the top silicon layer; depositing a first layer of material on the gate oxide layer; removing the first layer of material, the gate oxide layer and the top silicon layer from a device field region; forming an insulating cup about the first layer of material, the gate oxide layer and the top silicon layer; depositing a second layer of material over the first layer of material and the insulating cup; etching the first layer of material and the second layer of material to form a gate electrode; implanting ions to form a source region and a drain region; passivating the structure; and metallizing the structure.

Abstract: A method has been provided for forming a polycrystalline silicon (p-Si) film with a small amount of hydrogen. Such a film has been found to have excellent sheet resistance, and it is useful in the fabrication of liquid crystal display (LCD) panels made from thin film transistors (TFTs). The low hydrogen content polycrystalline silicon films are made from introducing a small amount of hydrogen gas, with Ar, during the sputter deposition of an amorphous silicon film. The hydrogen content in the film is regulated by controlling the deposition temperatures and the volume of hydrogen in the gas feed during the sputter deposition. The polycrystalline silicon film results from annealing the low hydrogen content amorphous silicon film thus formed.

Abstract: A method is provided for maintaining a planar surface as crystal grains are laterally grown in the fabrication of crystallized silicon films. The method comprises: forming a film of amorphous silicon with a surface and a plurality of areas; irradiating each adjacent areas of the silicon film with a first sequence of laser pulses; and, in response to the first sequence of laser pulses, controlling the planarization of the silicon film surface between adjacent areas of the silicon film as the crystal grains are laterally grown. By controlling the number of laser pulses in the sequence, the temporal separation between pulses, and the relative intensity of the pulses, the lateral growth length characteristics of the crystal grains can be traded against the silicon film flatness. A silicon film formed by a pulsed laser sequence crystallization process is also provided.

Abstract: A method for is provided forming a thin-film transistor (TFT) on a flexible substrate. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, stainless steel, or Kovar, having a thickness in the range of 10 to 500 microns; depositing and annealing amorphous silicon to form polycrystalline silicon; and, thermally growing a gate insulation film overlying the polycrystalline. The silicon annealing process can be conducted at a temperature greater than 700 degrees C. using a solid-phase crystallization (SPC) annealing process. Thermally growing a gate insulation film includes: forming a polycrystalline silicon layer having a thickness in the range of 10 to 100 nanometers (nm); and, thermally oxidizing the film at temperature in the range of 900 to 1150 degrees for a period of time in the range of 2 to 60 minutes. Alternately, a plasma oxide layer is deposited over a thinner thermally oxidized layer.

Abstract: A method is provided to deposit and pattern a sacrificial polymer, and form metal layers. A double hard mask is used to pattern and etch the sacrificial polymer. The double hard mask may be formed at temperatures below 400° C. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.

Abstract: A method is provided to produce thin polycrystalline films having a single predominant crystal orientation. The method is well suited to the production of films for use in production of thin film transistors (TFTs). A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lateral-seeded excimer laser annealing (LS-ELA) is used to crystallize the amorphous silicon to form a film with a preferred crystal orientation. The crystallized film is then polished to a desired thickness for subsequent processing.

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract: A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) process is provided for depositing one or more dielectric material layers on a substrate for use in interconnect structures of integrated circuits. The method comprises the steps of depositing a fluorinated amorphous carbon (a-F:C) layer on a substrate by providing a fluorine containing gas, preferably octafluorocyclobutane, and a carbon containing gas, preferably methane, in ratio of approximately 5.6, so as to deposit a a-F:C layer having an internal compressive stress of approximately 28 MPa. After deposition the film is annealed at approximately 400° C. for approximately two hours. An adhesion promoter layer of relatively hydrogen-free hydrogeneated silicon carbide is then deposited on the a-F:C layer using silane (SiH4) and methane (CH4) as the deposition gases.

Abstract: A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.

Abstract: A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Abstract: A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.

Abstract: A method has been provided for etching adjoining layers of indium tin oxide (ITO) and silicon in a single, continuous dry etching process. A conventional dry etching gas, such as HI, is used to etch ITO using RF or plasma energy. When the silicon layer underlying the ITO layer is reached, oxygen or nitrogen is added to etching gas to improve the selectivity of ITO to silicon. In some aspects of the invention an etch-stop layer is formed in the silicon layer. A specific example of fabricating a bottom gate thin film transistor (TFT) is also provided where adjoining layers of source metal, ITO, and channel silicon are etched in the same dry etch step.

Abstract: A metal gate complementary metal oxide semiconductor (CMOS) and a method of manufacturing the same is disclosed. The method includes depositing the metal gate electrode material as a final step before metallization of the device. Accordingly, the metal gate material is not subject to contamination during the fabrication process. The device is fabricated without the use of oxide spacers so that the finished device does not suffer from silicon faceting at the active silicon-to-shallow-trench-isolation-interface. Moreover, the dummy gate material is used to define planarization stops that allow precise planarization of the device during fabrication.

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract: A TFT fabricated from a single crystal grain, and fabrication method has been provided. A large crystal grain is made by precise control of annealment, transition metal concentration, the density of transition metal nucleation sites, and the distance between nucleation sites. In one aspect of the invention, a diffusion layer permits the continual delivery of transition metal at a rate that both supports the lateral growth of di-silicide, and large distances between nucleation sites.

Abstract: A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

Abstract: A CMOS transistor is formed on a single crystal silicon substrate. Active regions are formed on the substrate, including an nMOST active region and a pMOST active region. An epitaxial layer of undoped silicon is formed over the active regions. Out-diffusion from the underlying active regions produces dopant densities within the epitaxial layer one, or more, orders of magnitude lower than dopant densities within the underlying active regions. In a preferred embodiment, the epitaxial layer is counter doped by implanting ions of the opposite type to those within the underlying active region. Counter doping further reduces the dopant density, to reduce the threshold voltage further.

Abstract: A method for an efficient extended pulse laser annealing process is provided. The method comprises: supplying a substrate with a thickness; selecting an energy density; selecting an extended pulse duration; laser annealing a substrate region; in response to cooling the substrate region, crystallizing the substrate region; and, efficiently extending the lateral growth of crystals in the substrate region. When the substrate has a thickness of approximately 300 Å, the energy density is selected to be in the range of 400 to 500 millijoules pre square centimeter (mJ/cm2). The pulse duration is selected to be in the range between 70 and 120 nanoseconds (ns). More preferably, the pulse duration is selected to be in the range between 90 and 120 ns. Most preferable, the pulse duration is approximately 100 ns. Then, efficiently extending the lateral growth of crystals in the substrate region includes laterally growing crystals at a rate of approximately 0.029 microns per nanosecond.