Abstract: Embodiments of the present invention provide systems and methods for converting a higher-resolution image to a lower-resolution image with reduced visible errors. These embodiments comprise splitting a higher-resolution opponent color domain (OCD) image into separate initial luminance and initial chrominance channels followed by sub-pixel sampling on said initial luminance channel thereby creating an additive color domain (ACD) luminance image. This ACD luminance image is then converted into an OCD luminance image and split into separate sub-pixel sampled (SPS) luminance and SPS chrominance channels. The SPS chrominance channels are high-pass filtered and the initial chrominance channels are low-pass filtered. The filtered initial chrominance channels are sub-sampled and combined with the high-pass filtered SPS chrominance channels. These combined chrominance channels are then combined with said SPS luminance channel to form an error-reduced lower-resolution image.

Abstract: A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

Abstract: A method for chemical vapor deposition of copper metal thin film on a substrate includes heating a substrate onto which the copper metal thin film is to be deposited in a chemical vapor deposition chamber; vaporizing a precursor containing the copper metal, wherein the precursor is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene; introducing the vaporized precursor into the chemical vapor deposition chamber adjacent the heated substrate; and condensing the vaporized precursor onto the substrate thereby depositing copper metal onto the substrate. A copper metal precursor for use in the chemical vapor deposition of a copper metal thin film is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene taken from the group of alkenes consisting of 1-pentene, 1-hexene and trimethylvinylsilane.

Abstract: A method has been provided for the removal of oxidation from a substrate surface formed as the result of an ozone cleaning process in the fabrication of a liquid crystal display (LCD). A first method uses a dry etchant, such as CL2 gas, to remove the ozone oxidation layer. A second method uses a counter sputtering process to remove the ozone oxidation layer.

Abstract: A method is provided to optimize the channel characteristics of thin film transistors (TFTs) on polysilicon films. The method is well suited to the production of TFTs for use as drivers on liquid crystal display devices. Regions of polycrystalline silicon can be formed with different predominant crystal orientations. These crystal orientations can be selected to match the desired TFT channel orientations for different areas of the device. The crystal orientations are selected by rotating a mask pattern to a different orientation for each desired crystal orientation. The mask is used in connection with lateral crystallization ELA processes to crystallize deposited amorphous silicon films.

Abstract: A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

Abstract: A method of making a precursor for a thin film formed by chemical vapor deposition processes, includes mixing ZCl4 with H(tmhd)3 solvent and benzene to form a solution, where Z is an element taken from the group of elements consisting of hafnium and zirconium; refluxing the solution for twelve hours in an argon atmosphere; removing the solvents via vacuum, thereby producing a solid compound; and sublimating the compound at 200° C. in a near vacuum of 0.1 mmHg. A ZOx precursor, for use in a chemical vapor deposition process, includes a Z-containing compound taken from the group of compounds consisting of ZCl(tmhd)3 and ZCl2(tmhd)2.

Abstract: A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

Abstract: A method of monitoring the synthesis of a PGO spin-coating precursor solution includes monitoring heating of the solution with a UV spectrometer and terminating the heating step when a solution property reaches a predetermined value. The method utilizes the starting materials of lead acetate trihydrate (Pb(OAc)2.3H2O) and germanium alkoxide (Ge(OR)4 (R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol)ethyl ether. The mixed solution of lead and di(ethylene glycol)ethyl ether is heated in an atmosphere of air at a temperature no greater than 190° C., and preferably no greater than 185° C. for a time period in a range of approximately eighty-five minutes. During the heating step the solution properties are monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol)ethyl ether to make the PGO spin-coating solution.

Abstract: A method is provided for forming a 1T1R resistive memory array. The method of forming a 1T1R resistive memory array structure on a semiconductor substrate comprises forming an array of transistors comprising a polycide/oxide/nitride gate stack with nitride sidewalls, the transistors comprising a source and a drain region adjacent to the gate stack. An insulating layer is deposited and planarized level with the polycide/oxide/nitride gate stack. Bit contact openings are etched to expose the drain region. Bottom electrodes are formed by depositing and planarizing a metal. A resistive memory material is deposited over the bottom electrodes. Top electrodes are formed over the resistive memory material. The 1T1R resistive memory array may be connected to support circuits that are formed on the same substrate as the memory array. The support circuits may share many of the process steps with the formation of the transistors for the memory array.

Abstract: A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.

Abstract: A fabrication process provides for achieving high adhesion of CVD copper thin films on metal nitride substrates, and in particular, on substrates having an outermost TaN layer. The method comprises introducing a certain amount of water vapor to the initial copper thin film deposition stage and reducing the amount of fluorine in the interface of the copper and metal nitride substrate. These two process steps result in a copper thin film having improved adhesion to metal nitride substrates, including TaN substrates.

Abstract: The invention provides an apparatus for reducing, or eliminating, ambient air in connection with an excimer laser annealing process. Nozzles are provided to direct a flow of gas, preferably helium, neon, argon or nitrogen, at a region overlying the target area of an amorphous silicon layer deposited on an LCD substrate. The nozzles direct a flow of gas at sufficient pressure and flow rate to remove ambient air from the region overlying the target area. With the ambient air, especially oxygen, removed, the laser can anneal the amorphous silicon to produce polycrystalline silicon with less oxygen contamination. In a preferred embodiment, an exhaust system is also provided to remove the gas.

Abstract: A system and method are provided to sequentially deposit a silicon dioxide base coat barrier layer adjacent a thin silicon film, to minimize the formation of water and —OH radicals. Both the base coat and thin silicon films are sputter to eliminate hydrogen chemistries. Further, the sputter processes are conducted sequentially, without breaking the vacuum seat to minimize the absorption of water in the base coat layer that conventionally occurs between deposition steps. This process eliminates the total number of process steps required, as there is no longer a need for furnace annealing the base coat before the deposition of the thin silicon film, and no longer a need for a dehydrogenation annealing step after the deposition of the thin silicon film.

Abstract: A method of forming a highly adhesive copper thin film on a metal nitride substrate includes preparing a substrate having a metal nitride barrier layer formed on a portion thereof; heating the substrate in a chemical vapor deposition chamber to a temperature of between 160° C. to 250° C. for about one minute and simultaneously introducing a copper precursor into the reaction chamber at a very slow initial flow rate of between less than 0.1 ml/min, and simultaneously providing an initial high wet helium gas flow in the reaction chamber of greater than or equal to 5 sccm; reducing the wet helium gas flow in the reaction chamber to less than 5 sccm; and increasing the flow of copper precursor to between about 0.1 ml/min and 0.6 ml/min.

Abstract: A method of forming a copper thin film by chemical vapor deposition, includes introducing a wafer into a chemical vapor deposition chamber; humidifying helium gas with water to form a wet helium gas for use as the atmosphere in the chemical vapor deposition chamber; depositing a copper seed layer at a wet helium flow rate of between about 5.0 sccm and 20.0 sccm during a wafer temperature rise from ambient temperature to between about 150° C. to 230° C.; and depositing a copper thin film layer at a wet helium flow rate of between about 0.2 sccm to 1.0 sccm and at a temperature of between about 150° C. to 230° C.

Abstract: A method is provided to optimize the channel characteristics of thin film transistors (TFTs) on polysilicon films. The method is well suited to the production of TFTs for use as drivers on liquid crystal display devices. The method is also well suited to the production of other devices using polysilicon films. Regions of polycrystalline silicon can be formed with different predominant crystal orientations. These crystal orientations can be selected to match the desired TFT channel orientations for different areas of the device. The crystal orientations are selected by selecting different mask patterns for each of the desired crystal orientation. The mask patterns are used in connection with lateral crystallization ELA processes to crystallize deposited amorphous silicon films.

Abstract: A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

Abstract: A shared bit line cross point memory array structure is provided, along with methods of manufacture and use. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross point is formed between the bottom word line and the bit line and a second cross point is formed between the bit line and the top word line. A material having a property, for example resistance, that can be changed in response to an input voltage is provided at each cross point above and below the bit line.

Abstract: A method of making a ferroelectric memory transistor includes preparing a silicon substrate including forming plural active areas thereon; depositing a layer of gate insulator on the substrate, and depositing a layer of polysilicon over the gate insulator layer; forming a source region, a drain region and a gate electrode; depositing a layer of bottom electrode material and finishing the bottom electrode without damaging the underlying gate insulator and silicon substrate; depositing a layer of ferroelectric material on the bottom electrode; depositing a layer of top electrode material on the ferroelectric material; and finishing the transistor, including passivation oxide deposition, contact hole etching and metalization.