Abstract: A method of forming carbon nanotubes includes incorporating phosphors in the form of quantum dots, along with the beads of ZnO on carbon nanotubes (CNTs) to generate white light. The ability to form a high density of quantum dots in a small volume allows for a high probability of UV absorption and subsequent re-emission to generate visible radiation. The material and size of the quantum dots can be controlled by an atomic layer deposition (ALD) process and thermal cycle.

Abstract: A method of forming a layer of high-k dielectric material in an integrated circuit includes preparing a silicon substrate; forming a high-k dielectric layer by a sequence of ALD cycles including: depositing a first layer of metal ligand using ALD with an oxygen-containing first precursor; and depositing a second layer of metal ligand using ALD with a second precursor; repeating the sequence of ALD cycles N times until a near-critical thickness of metal oxide is formed; annealing the substrate and metal oxide layers every N ALD cycles in an elevated temperature anneal; repeating the sequence of ALD cycles and elevated temperature anneals until a high-k dielectric layer of desired thickness is formed; annealing the substrate and the metal oxide layers in a final annealing step; and completing the integrated circuit.

Abstract: A method generally for output handling a new imaging job, and specifically for handling such a job by delivering it to one of several currently job-engaged imaging output devices (illustrated as printers) including the steps of (a) examining the current job-processing statuses of such devices, and (b) from the result of that examining, determining the respective remainders in the amounts of current-job work still to be performed by those devices. The method thus features the acquisition and use of output device busyness information as an important part of the approach toward promoting efficient output handling of new imaging jobs.

Abstract: Disclosed herein is a method for performing ongoing ad hoc network topology discovery with regard to a collection of plural participating nodes. The method features the steps of (a) defining an appropriate topology-discovery condition to be associated with such nodes, (b) when that condition occurs, establishing and activating a dedicated, contention-free, discovery-communication time period wherein each node broadcasts, for reception by all other nodes, its attributes, including its identity, it operating characteristics, its capabilities, and its associated link qualities in relation to the other nodes, (c) utilizing the results of such establishing and activating steps, creating an overall network topology map associated with the nodes, and (d) then making that map available for use in subsequent network organizational activities, including the practices of creating suitable communication links between nodes, and enabling organization of a network into appropriate subnets and proxy networks.

Abstract: A method of fabricating a grayscale reticule includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticule; and using the reticule to pattern a microlens array.

Abstract: A scheduling system for an MFP to provided scheduled readiness of the MFP includes an MFP having an EMail address associated therewith; an EMail system for generating user EMAILS and transmitting the generated EMAILS; a readiness specification which is contained in a user-generated EMail and which sets parameters controlling the readiness of the MFP; an acknowledgment mechanism in the MFP for generating a reply EMail, indicating that the readiness specification has been received and entered; and an error message generator in the MFP for generating a reply EMail indicating that the readiness specification has not been entered.

Abstract: Ringing artifacts are removed from a quantized image by an image de-ringing filter that includes a determination unit, an adaptive filter and a nonlinear low-pass filter. The determination unit determines whether each selected pixel of a first set of selected pixels of an image contains a ringing artifact based on, for example, gray-level values of selected pixels within a determination kernel of pixels relating to the selected pixel. The adaptive filter generates a filtered gray-level value for each pixel determined by the determination unit to contain a ringing artifact based on, for example, gray-level values of selected pixels within a filtering kernel of pixels relating to the pixel. The nonlinear low-pass filter generates a low-pass-filtered gray-level value for each selected pixel of a second set of selected pixels of the image.

Abstract: A method and apparatus employable in a wireless, packet-based network communication system for managing transmission-limit build-up performed by participating network BSS stations, whereby, when singular ones (one only) of these stations, during a given transmission budget beacon interval, are attempting to gain access to network transmission bandwidth, they are permitted to invoke an algorithm for rapid transmission-limit build-up. Such rapid build-up is based upon allowing such a station to begin its accessing process with an elevated, initial transmission limit which is created as a relatively high percentage (preferably about 80-percent) of the last prior beacon-announced network transmission budget. If more than one such currently non-transmitting stations are simultaneously attempting anew to gain network bandwidth access, rapid build-up is not permitted, thus to minimize an otherwise possible network communication traffic jam.

Abstract: A method and apparatus employable in a wireless, packet-based network communication system for managing transmission-limit build-up performed by participating network BSS stations, whereby, when singular ones (one only) of these stations, during a given transmission budget beacon interval, are attempting to gain access to network transmission bandwidth, they are permitted to invoke an algorithm for rapid transmission-limit build-up. Such rapid build-up is based upon allowing such a station to begin its accessing process with an elevated, initial transmission limit which is created as a relatively high percentage (preferably about 80-percent) of the last prior beacon-announced network transmission budget. If more than one such currently non-transmitting stations are simultaneously attempting anew to gain network bandwidth access, rapid build-up is not permitted, thus to minimize an otherwise possible network communication traffic jam.

Abstract: A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.

Abstract: A vector error diffusion (VED) method employable in cycles with respect to a hi-tonal color printing engine which prints bi-tonal color images in a device output color space. The method generally includes (a) acquiring input color-image data which is characterized with an input color space, (b) processing, with available pre-established VED accumulated error data, such input data to produce a VED-processed input color-image data stream, (c) from such VED-processed input color-image data stream, creating, without employing interpolation, a VED-processed output color-image data stream which is characterized by the mentioned device output color space, and which is suitable for delivery to and use by the mentioned printing engine, and (d) changing, as appropriate for the next cycle, the VED accumulated error data which will be employed in that next cycle as pre-established VED accumulated error data.

Abstract: A method of fabricating a RRAM includes preparing a substrate and forming a bottom electrode ori the substrate. A PCMO layer is deposited on the bottom electrode using MOCVD or liquid MOCVD, followed by a post-annealing process. The deposited PCMO thin film has a crystallized PCMO structure or a nano-size and amorphous PCMO structure. A top electrode is formed on the PCMO layer.

Abstract: A method of fabricating a multi-level 3D memory array includes: preparing a wafer and peripheral circuits thereon; layers of metal, memory resistor material, and metal are deposited, patterned and etched. The steps of the method of the invention are repeated for N levels of a memory array.

Abstract: The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide transistor can have great potential in ferroelectric non volatile memory device with the further advantages of good interfacial properties with the ferroelectric materials, possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem to improve the reliability of the ferroelectric memory transistor. The semiconductive metal oxide film is preferably a metal oxide exhibiting semiconducting properties at the transistor operating conditions, for example, In2O3 or RuO2.

Abstract: A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

Abstract: A method of fabricating a germanium photo detector includes preparing a silicon substrate wafer and depositing and planarizing a silicon oxide layer on the silicon substrate. Contact holes are formed in the silicon oxide layer. An N+ epitaxial germanium layer is grown on the silicon oxide layer and in the contact holes. An N+ germanium layer is formed by ELO. The structure is smoothed and thinned. An intrinsic germanium layer is grown on the N+ epitaxial germanium layer. A P+ germanium layer is formed on the intrinsic germanium layer and a silicon oxide overcoat is deposited. A window is opened through the silicon oxide overcoat to the P+ germanium layer. A layer of conductive material is deposited on the silicon oxide overcoat and in the windows therein. The conductive material is etched to form individual sensing elements.

Abstract: A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation of a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on a silicon substrate; depositing a layer of refractory metal; treating the surfaces of the donor wafer and the handling wafer for bonding; bonding the handling wafer and the donor wafer to form a bonded structure; splitting the bonded structure along the defect layer; depositing a layer of indium tin oxide on the germanium layer; completing the IR sensor.

Abstract: A method of providing backwards compatibility of a new TDMA system with an existing CSMA/CA system, wherein the CSMA/CA system includes asynchronous packet transmission, and wherein the TDMA system includes synchronous packet transmission, and wherein both systems transmit and receive over the same communication channel, including providing a control coordinator; dividing the TDMA system's frame into sub-frames for use by the CSMA/CA system and the TDMA system; and generating delimiters by the control coordinator to gain, retain and relinquish control of the communication channel from the CSMA/CA system, and wherein the delimiters are transmitted during guard bands of the TDMA system.

Abstract: A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a portion of the SiGe layer; depositing a dielectric on the silicon side of the silicon-on-glass wafer; applying adhesive and bonding a plastic substrate to the silicon side of the silicon-on-glass wafer; removing the glass from the glass side of the bonded, silicon-on-glass wafer to form a silicon-on-plastic wafer; and completing a desired IC device on the silicon-on-plastic. Multi-level structure may be fabricated according to the method of the invention by repeating the last few steps of the method of the invention.

Abstract: A method of etching an iridium layer for use in a ferroelectric device includes preparing a substrate; depositing a barrier layer on the substrate; depositing an iridium layer on the barrier layer; depositing a hard mask layer on the iridium layer; depositing, patterning and developing a photoresist layer on the hard mask; etching the hard mask layer; etching the iridium layer using argon, oxygen and chlorine chemistry in a high-density plasma reactor; and completing the ferroelectric device.