Abstract: Method and apparatus for varying the output signal frequency of a controlled oscillator. The oscillator control signal is formed by filtering the output of a random number generator in such a way that the oscillatory output signal has a random frequency walk phase characteristic having predetermined, controlled characteristics.

Abstract: A random access memory cell includes a volatile RAM cell, a non-volatile RAM cell and a transfer control circuit connected between the volatile and non-volatile elements. The volatile element includes two nodes and has two stable states. The non-volatile element also includes two nodes, each of which is connected to one of the nodes of the volatile element. The non-volatile element preferably includes a floating gate field effect transistor used as a storage transistor and connected between the two nodes of the non-volatile element to store a charge corresponding to the state of the non-volatile element. A second floating gate field effect transistor is coupled to the storage transistor to be used as a sense transistor. The transfer control circuit selectively connects the sense transistor to one of the nodes of the volatile element to cause the volatile element to adopt the state represented by the charge on the storage transistor of the non-volatile element.

Abstract: A method and apparatus for multiplying two digital pairings representing complex numbers is described. The method includes preloading a memory with contents based on the second complex combination and the basis vector, and repeatedly addressing the memory based on the first complex combination taken L bits at a time in order to accumulate a complex product combination. The complex multiplication apparatus is preferably constructed as high speed circuitry on a gallium arsenide integrated circuit chip.

Abstract: A method of providing a planar or iso-planar surface to the interlevel dielectric layer between metal layers of a multilevel MOS wafer includes applying a first dielectric over the first metal layer, applying a layer of spin-on glass over the first dielectric layer, etching the spin-on glass layer in an etch process in which the rate of etch of the spin-on glass is approximately the same as the rate of etch of the first dielectric to reveal at least a portion of the first dielectric layer. A second dielectric layer is placed over the surface of the first dielectric. Vias may then be defined through the dielectric layers, and the second metal layer may be applied over the relatively smooth surface of the second dielectric layer.

Abstract: Method and apparatus for varying the output signal frequency of a controlled oscillator. The oscillator control signal is formed by filtering the output of a random number generator in such a way that the oscillatory output signal has a random frequency walk phase characteristic having predetermined, controlled characteristics.

Abstract: A modem having automatic gain control update circuitry for use with CCITT Group II facsimile machines. The update circuitry receives incoming facsimile data samples, averages the samples for predetermined periods, compares the averages to find the maximum during each line of facsimile data, and updates a gain control to accommodate the maximum found. The update circuitry allows the modem automatic gain control to operate without the use of external synchronization strobe signals, and has an optional selectable fast automatic gain control adjustment mode.

Abstract: De-glitch circuitry selectively responds to the time duration of actuation signals for selecting between pages in a read only memory. The de-glitch circuitry uses MOSFET transistors to act as resistors and capacitors in order to provide an RC time constant. The RC time constant is selected to allow the de-glitch circuitry to eliminate spurious glitches and prevent unwanted segment selections in the memory. The de-glitch circuitry is used with a voltage reference generator, segment selection decoders, sense amplifiers, and a flip-flop; all of which are constructed of MOSFET transistors and incorporated in a read only memory integrated circuit chip. The de-glitch circuitry is particularly useful in the construction of program cartridges for video game computer systems.

Abstract: In a data communications network having a plurality of information processing sytems coupled to a communication channel which serially transmits data in the form of information packets, a network controller is provided between the communication channel and an information processing system. The network controller includes a counter connected to the transmit buffer for controlling the release of packets from the transmit buffer according to a predetermined amount of time between the transmission of successive packets.

Abstract: A network controller includes an interface unit connected to a communication network channel for transferring data in the form of information packets to and from the channel; a receive buffer connected for storing in parallel form the data packets transferred from the communication channel; and first and second shift registers having n bit positions including a pointer bits to the receive buffer, circulating at different clock rates corresponding to the clock rate of data on said communication channel and the clock rate of the system bus.

Abstract: A silicon on sapphire (SOS) semiconductor structure may be processed to improve the electrical characteristics of a silicon film on a sapphire substrate by silicon-regrowth (SRG) techniques using oxidation to remove silicon from the outward surface of the silicon film. An epitaxial film on a sapphire substrate is implanted with silicon to amorphize the silicon film except for a thin seed layer on the outward surface of the silicon film. The silicon is recrystallized inwards using the seed layer as a seed for crystallization. The silicon film is oxidized to produce an oxide layer on the outward surface of the silicon film, the SOS structure may be heated to densify the oxide layer, and the oxide layer is etched away. This produces a silicon film with a reduced p-type electrical activity and improved crystalline quality surface so that the channel mobility is improved for semiconductor devices fabricated in the silicon film.

Abstract: A circuit for use on an integrated circuit chip for detecting the operative connection of a crystal used to control an on-chip crystal controlled oscillator, which generates a cyclical clock signal, by detecting the presence or absence, respectively, of the cyclical clock signal and for providing an output control signal in response thereto to an on-chip terminal pad control circuit which automatically enables an on-chip terminal pad to be utilized as a clock signal output terminal pad if the cyclical clock signal presence is detected or as a clock signal input terminal pad otherwise. Also, a method of automatically switching the function of a terminal pad on an integrated circuit chip to function as a clock signal output terminal pad or as a clock signal input terminal pad in accordance with detecting the existence or non-existence of a cyclical clock signal generated on-chip.

Abstract: A signal processing device for the correction of signal amplitude distortion occurring in a plurality of signalling channels such as obtained from a detector array in which each detector has a different non-uniform response. Compensatory amplitude adjustment is made to each sampled signal in accordance with the statistical deviation of the signal from a preselected statistical model. A signal sampling device employs each sampled signal as a write-address for generating a statistical amplitude distribution function. Inverse distribution function means, responsive to addressing by the distribution function, provides an output signal of compensatorily modified amplitude for each signal sample.

Abstract: A microcomputer interval counter circuit for detecting the time interval between input signals and for determining when the detected time interval exceeds a preset time interval.The interval counter circuit includes a latch connected to a bus of the microcomputer for storing the preset time interval duration, a counter circuit connected to the latch and to the microcomputer clock for decrementing a number stored in the counter and producing a timing indication as an interrupt to the microcomputer processor, and an OR gate connected to load the counter from the latch when an input signal is received, or when the counter circuit fully decrements.

Abstract: A transversal adaptive filter with a tap weight computer having a respective first and second input responsively coupled to a respective output and input of the filter, and including spectrum shaping means. The spectrum shaping means comprises matched or like preselected bandpass means interposed at the inputs of the tap weight computer.