Abstract: An embodiment of the present invention depicts a storage capacitor comprising: a bottom plate structure having a hemispherical grain silicon surface; a titanium nitride layer adjacent and coextensive the hemispherical grain silicon; an insulating layer adjacent and coextensive the titanium nitride layer; and a top plate structure comprising conductively doped polysilicon layer superjacent and coextensive the insulating layer.

Abstract: The present invention develops a process for forming hemi-spherical grained silicon storage capacitor plates by the steps of: forming a silicon layer over a pair of neighboring parallel conductive lines, the silicon layer making contact to an underlying conductive region; patterning the silicon layer to form individual silicon capacitor plates; exposing the silicon capacitor plates to a fluorine based gas mixture during an high vacuum annealing period, thereby transforming the silicon capacitor plates into the semi-spherical grained silicon capacitor plates; conductively doping the hemispherical grained silicon capacitor plates; forming a capacitor dielectric layer adjacent and coextensive the semispherical grained silicon capacitor plates; and forming a second conductive silicon layer superjacent and coextensive the capacitor dielectric layer.

Abstract: A simple trip-wire or magnetic circuit associated with a shipping container monitors continuity, which is detected electrically. Simply, if continuity is disabled by a forced entry of the container, electrical detection means, such as a radio-frequency-identification (RFID) tag, will alert the owner or monitoring station. The trip-wire concept would require the replacing of a broken trip wire (resulting from forced entry), while the magnetic circuit concept can be reused repetitively. In a second embodiment a magnetic circuit and the detection device (RFID tag) are embedded into the shipping article during manufacturing. The preferred detection device, an RFID tag, could also be a battery backed transceiver type on which a replaceable or rechargeable battery could be mounted on the inside of the shipping container during manufacturing. The RFID tag would communicate with an interrogator unit, which could be connected to a host computer.

Abstract: The present invention develops a bond pad interconnect in an integrated circuit device, by forming an aluminum pad; bonding a metal layer (such as copper (Cu), nickel (Ni), tungsten (W), gold (Au), silver (Ag) or platinum (Pt)) or a metal alloy (such as titanium nitride) to the aluminum bond pad by chemical vapor deposition or by electroless deposition; and adhering a conductive epoxy film to the metal layer, thereby forming a low resistive bond pad interconnect.

Abstract: The present invention is a Static Random Access Memory fabrication process for forming a buried contact, by the steps of: patterning a photoresist layer over the field silicon dioxide regions and the spaced apart areas of the substrate, thereby providing a buried contact implant window to expose a portion of at least one spaced apart area and an adjacent field silicon dioxide end portion; implanting an N-type dopant through the buried implant contact window, the implant forming a first N-type diffusion region in the exposed spaced apart area and changing the etch rate of the exposed field silicon dioxide end portion; stripping the masking layer; growing a sacrificial silicon dioxide layer, over the field silicon dioxide regions and the spaced apart areas of the supporting silicon substrate, thereby annealing the exposed field silicon dioxide end portion and returning the etch rate of the exposed field silicon dioxide end portion to substantially the same etch rate as prior to the implantation step; stripping

Abstract: A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: A method of fabricating a stacked capacitor memory cell having a reduced leakage storage node includes the steps of providing a P-type substrate, forming wordlines on a thin gate oxide layer and a field oxide layer, and forming a first conformal TEOS oxide layer. The P-type substrate is doped with an N-type dopant directly through the first TEOS oxide layer to form two N-type diffused areas, which are the first and second current terminals of the memory cell access transistor. A second conformal TEOS oxide layer is deposited. The oxide layers are etched to form a buried contact window above the storage node of the memory cell. The exposed portion of the N-type diffused area forming the memory cell storage node is subsequently doped with germanium through the buried contact window to suppress any outdiffusion due to the doping of subsequently formed layers, such as the first plate of a stacked polysilicon capacitor.

Abstract: The method of the present invention introduces a fabrication method for forming a storage capacitor on a supporting silicon substrate of a semiconductor device, by the steps of: forming a bottom capacitor electrode comprising conductively doped polysilicon; forming an insulating layer over the bottom electrode via a first rapid thermal processing step (RTP) using rapid thermal silicon nitride (RTN); forming a capacitor dielectric material comprising tantalum oxide (Ta.sub.2 O.sub.5) over the insulating layer; forming a semiconductive layer comprising polysilicon over the capacitor dielectric material; converting the semiconductive layer into a reaction prevention barrier by subjecting the semiconductive layer to a second rapid thermal processing step (RTP) using rapid thermal silicon nitride (RTN); and forming a top capacitor conductive electrode comprising titanium nitride (TiN) over the reaction prevention barrier.

Abstract: The basic concept of the present invention comprises converting a standard buffer circuit into an adjustable buffer circuit that will in effect reduce the operating speed and power consumption of the IC in which it is constructed. An adjustable buffer circuit can be designed into a chip design that will allow manufacturing to either use a bonding option or the blowing of a fuse to adjust its operating speed and active power consumption. One important application would be in memory devices such as for static random access memory (SRAM) devices. For example, if may be desirable to allow a -15 ns access time SRAM to be downgraded to a -20 ns or -35 ns access time device while lowering its active power consumption by .apprxeq.20-30% so that it will pass the -35 ns I.sub.CC specification rating.

Abstract: The CMOS voltage compensating input buffer circuit of the present invention provides a means to stabilize input level trip points and is comprised of a voltage compensating circuit having an input node and an output drive node coupled to an input buffer. The voltage compensating circuit receives its input from a voltage adjusting circuit that follows changes in V.sub.CC while its output drive node is coupled to the series connected CMOS input buffer circuit having an input node and an output node. The buffer's input node receives a signal that VIH/VIL trip points will determine if the output is to be a high or a low and the buffer's output node then couples the resultant level to an output buffer circuit comprised of a CMOS inverter which provides the final output drive. The present invention provides trip point levels corresponding to industry standard VIH/VIL levels to accurately determine the corresponding output with operating voltage supplies (regulated or unregulated) operating between 2 V to 7.5 V.

Abstract: The present invention provides a method for forming conductive container structures on a supporting substrate of a semiconductor device, by: forming an insulating layer over parallel conductive lines and existing material on the surface of the supporting substrate; providing openings into the insulating layer, the openings forming vertical sidewalls in the insulating layer that resides between two neighboring conductive lines and thereby exposing an underlying conductive material; forming a sacrificial layer that makes contact with the underlying conductive material; forming a barrier layer overlying and conforming to the sacrificial layer; forming insulating spacers on the vertical sidewalls of the barrier layer; removing portions of the barrier layer and the sacrificial layer that span between the insulating spacers to thereby expose a portion of the underlying conductive material; removing the insulating spacers and thereby exposing the barrier layer; forming a conductive layer that conforms to the exposed

Abstract: The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.

Abstract: A process for forming low resistance contacts between silicide areas and upper level polysilicon interconnect layers including a specific doping technique that provides solid low resistance contacts between a lower level of a silicided area and an upper level polysilicon interconnect. The doping technique combines a doping implant of the upper level polysilicon and an ion-mixing implant into a single implant thereby achieving a low resistive implant which also reduces processing steps.

Abstract: The present invention provides production repeatable process to form polysilicon storage node structures using MVP technology. The storage node is formed over word lines beginning with a deposition and planarization of an insulator or composite insulator. A contact/container photo and etch creates a contact/container opening to provide access to the underlying active area either directly or through a conductive plug. After the contact/container opening is formed, an insitu doped polysilicon layer is deposited and planarized to completely fill contact/container opening while isolating adjacent storage nodes from one another. Next an oxide layer is deposited and is followed by deposition of HSG poly. Then a plasma poly etch of the HSG poly is performed that is followed by a plasma oxide etch. After these steps, a timed poly etch is performed long enough to sufficiently transfer an `archipelago` pattern to storage node poly.

Abstract: The present invention develops a container capacitor by forming a conductively doped polysilicon plug between a pair of neighboring parallel conductive word lines; forming a planarized tetra-ethyl-ortho-silicate (TEOS) insulating layer over the parallel conductive word lines and the plug; forming a planarized borophosphosilicate glass (BPSG) insulating layer over the planarized tetra-ethyl-ortho-silicate (TEOS) insulative layer; forming an opening into both insulating layers to expose an upper surface of the plug, the opening thereby forming a container shape; forming first, second and third layers of conductively doped amorphous silicon into the container shape while simultaneously bleeding oxygen into the amorphous silicon; forming individual container structures having inner and outer surfaces and thereby exposing the BPSG insulating layer; removing the BPSG insulating layer thereby exposing the outer surface of the container structures; converting the exposed inner and outer surfaces of amorphous silicon

Abstract: The input ESD protection circuit of the present invention uses a series n+ active area resistor placed in an n-well placed in series with shunt transistor all of which are in parallel with an SCR shunt to ground circuit, thereby providing greater than +/-7000V HBM (the Mil. Std. human body model (HBM) test model) and +/-600V MM EIAJ (the EIAJ machine model (MM) test model) ESD protection response. The series n+ active area resistor is placed inside an n-well as are all metal contacts to the input, to improve junction integrity during an ESD event. The parallel SCR circuit is designed in a layout that has an n+ diffusion area tied to V.sub.SS surrounding the n+/p+ diffusion inside the n-well on three sides to provide greater surface area for current distribution.

Abstract: The invention is directed to a thin film transistor (TFT) fabricated by using a recessed planarized poly plug as the bottom gate and a recessed planarized poly plug for the TFT drain connecting region. The TFT of the present invention can be used in any integrated circuit that uses such devices and in particular as a pullup device in a static random access memory (SRAM). The invention is directed to a process to fabricate a thin film transistor (TFT) having LDDs and/or high resistive regions (loads) that are self-aligned to a recessed plug that is used as the bottom gate for the TFT.

Abstract: The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present invention provides some significant advantages, such as a lower programming voltage, which allows use of the DRAM's existing operating supply, and requiring only half of the operating voltage to test the element once programming is accomplished. The lower programming voltage allows for redundancy repair of defective DRAM cells (or selecting other options) to be made after the DRAM die is packaged including after it is installed at a customer's site.

Abstract: The present invention introduces a method of reducing conductive and convective heat loss from the battery unit in battery-powered devices, such as RFID tag devices. Battery heat loss prevention is accomplished by suspending the battery in a vacuum or within a low thermally conductivity gas, such as air, nitrogen, helium or argon. Further improvement is accomplished by using a minimum number of suspension points made of solid material which possesses a low thermally conductivity. The battery can be suspended by various means, the first of which totally encapsulates the battery using the minimum number of solid material suspension points mentioned above, and the second of which only a portion of the battery (such as the lower portion) is suspended in a low thermally conductive material and the upper portion is encapsulated by the low thermally conductive material fabricated in an arching structure that does not contact the upper portion of the battery.

Abstract: A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.