Abstract: A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of a polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: The present invention develops a process wherein a method for fabrication of field emission tips for flat panel displays and in particular to the formation of an array of self-aligned emission cathode tips. The method forms self-aligned ultra-sharp cathode tips out of a conducting material by etching contacts into an insulator which encloses a grid of conducting lines which will serve as the anodes. Next, a film having poor step coverage is deposited into the contacts followed by a selective deposition of a conducting material thereby resulting in a cone shaped configuration. Then the film is etched selective to the cone followed by the sharpening of the cone tip by conventional methods, thereby resulting in an array of evenly-spaced self-aligned emission cathodes having ultra-sharp tips.

Abstract: Disclosed is a process and structure for use with a Flash E.sup.2 PROM and EPROM. The inventive structure allows for positioning of the control gates over the active area in a manner which allows for more error in the process thereby increasing yields.

Abstract: A mini-stack capacitor process, developed for DRAM fabrication, is used to create a stacked capacitor by depositing multiple layers of dielectric over existing digit and word lines. The exposed top dielectric is then masked and etched away between two adjacent digit lines, the resist is stripped and subsequent etches (or etch) remove(s) the remaining dielectric layers thereby exposing the underlying conductively doped diffusion region. The storage node poly is then deposited and patterned, followed by subsequent depositions of a cell dielectric and cell plate poly. The selection of the number of dielectrics used and the type and/or sequence of dielectric etches used are the crux of the invention that substantially increases the surface area of a given stacked capacitor by approximately 40 to 80%.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked H-Cell (SHC). The SHC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SHC is made up of a polysilicon storage node structure having a H-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SHC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an H-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

Abstract: An improved CMOS voltage level translator circuit having an interface stage, an intermediate stage and an output stage is presented. The inventive circuit is characterized by low crossover current in the output and intermediate stages while maintaining minimal delay response when translating a lower potential signal into a higher potential signal. The improved translator circuit may be used in applications such as during EEPROM programming where control signals with normal voltage TTL voltage swing of V.sub.CC and V.sub.SS need to interface with the EEPROM row decoders which require a much higher voltage swing of V.sub.CC ' (>V hd CC) and V.sub.SS.

Abstract: The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines in a programmable read only memory. With a each digit line passing under each word line in a row/column matrix is formed thereby providing a programmable digit/word line matrix. Each crossing point of the digit and word lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word line conductors.

Abstract: A multi-poly spacer, double-plate, stacked capacitor or MDSC using a modified stacked capacitor storage cell fabrication process. The MDSC is made up of a rectangular boxed-shaped polysilicon storage node structure, having multiple poly post residing in a buried contact used to connect the MDSC to an active area. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed MDSC. Developing the MDSC from a planarized surface allows the capacitor to be fabricated with only 2 photomask steps. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 100% or more is gained at the storage node.

Abstract: A process for texturization of polycrystalline silicon comprising the steps of utilizing gas phase nucleation by injecting a material to a cause heterogeneous nucleation or by increasing deposition temperature or pressure to cause a homogeneous nucleation of the silicon source itself. Heterogeneous or homogeneous gas phase nucleation causes large, stable textures in the deposited polysilicon that can be doped using conventional fabrication techniques.

Abstract: The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present invention provides some significant advantages, such as a lower programming voltage, which allows use of the DRAM's existing operating supply, and requiring only half of the operating voltage to test the element once programming is accomplished. The lower programming voltage allows for redundancy repair of defective DRAM cells (or selecting other options) to be made after the DRAM die is packaged including after it is installed at a customer's site.

Abstract: A mushroom double stacked capacitor (mushroom cell) using a modified stacked capacitor storage cell fabrication process. The mushroom cell is made up of polysilicon structure, having a mushroom extended V-shaped cross-section. The storage node plate of the mushroom cell is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The shape of the polysilicon structure increases storage capability 200% or more without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

Abstract: A process for texturization of polycrystalline silicon comprising the steps of preparing the wafer surface prior to poly deposition with a material which will cause the poly to preferentially nucleate during deposition and form poly nodules on the wafer surface. Polysilicon will continue to coat the previously created poly nodules throughout poly deposition, thereby resulting in a stable, texturized polysilicon structure.

Abstract: A stacked surrounding reintrant wall capacitor (SSRWC) using a modified stacked capacitor storage cell fabrication process. The SSRWC is made up of polysilicon structure, having an elongated v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: A mushroom double stacked capacitor (mushroom cell) using a modified stacked capacitor storage cell fabrication process. The mushroom cell is made up of polysilicon structure, having a mushroom extended V-shaped cross-section. The storage node plate of the mushroom cell is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The shape of the polysilicon structure increases storage capability 200% or more without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Double Ring Stacked Cell or DRSC. The DRSC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The DRSC is made up of a polysilicon storage node structure having circular polysilicon ringed upper portion centered about a lower portion that makes contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed DRSC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having double polysilicon rings, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

Abstract: A stacked textured container capacitor (STCC) using a modified stacked capacitor storage cell fabrication process. The STCC is made up of a texturized polysilicon structure, having an elongated u-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. With the 3-dimensional shape and texturized surface of a polysilicon storage node plate substantial capacitor plate surface area of 200% or more is gained at the storage node.

Abstract: This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked cell capacitors using a PZT ferroelectric material as a storage cell dielectric for use in high-density dynamic random access memory (DRAM) arrays. The present invention employs using PZT ferroelectric for the storage cell dielectric in three-dimensional stacked capacitor technology and develops an existing stacked capacitor fabrication process to construct a PZT three-dimensional stacked capacitor cell (the EFSC) that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10X or more over that of a conventional 3-dimensional storage cell is gained by using PZT ferroelectric as the storage cell dielectric.

Abstract: An implant method to develop a storage node access MOSFET to a 3-dimensional stacked capacitor storage cell during a semiconductor fabrication process. This implant method utilizes one layer of oxide to serve as both a MOSFET's (N-channel or P-channel) lightly doped drain spacer as well as a subsequent polysilicon etch stopper when etching a FET's digitline. As DRAM density increases the use of only one oxide layer decreases oxide bridging or buildup.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to hereinafter as a stacked E cell or SEC. The SEC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SEC is made up of a polysilicon storage node structure having an E-shaped cross-sectional upper portion and a lower portion making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SEC capacitor. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 3 to 5X is gained at the storage node.

Abstract: A method of partially eliminating the field oxide bird's beak over a storage cell and slightly enlarging the storage cell active area without adding any process steps is described. A photomask is used during a buried contact etch to reduce the field oxide bird's beak both vertically and horizonally. The storage cell active area is further enlarged during a first polysilicon etch step without adding process steps. At that point, the wafer is completed by existing techniques.