Abstract: A self-aligned vertical intrinsic resistance for use in semiconductor devices is developed. The self-aligned vertical intrinsic resistance may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The vertical positioning of the intrinsic resistance not only takes up less die space but also allows for a simple process to construct the resistance by eliminating a photomask step that is normally required prior to implanting an intrinsic resistance used in conventional fabrication processes.

Abstract: A lateral extension stacked capacitor (LESC) using a modified stacked capacitor storage cell fabrication process. The LESC is made up of polysilicon structure, having a spherical ended v-shaped cross-section. The storage node plate of the LESC is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

Abstract: A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: A stacked comb spacer capacitor (SCSC) using a modified stacked capacitor storage cell fabrication process. The SCSC is made up of polysilicon structure, having a spiked v-shaped (or comb-shaped) cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The creation of the spiked polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell. Removing the dielectric residing under the backside of the storage node cell plate and filling that area with polysilicon increases storage capacity by an additional 50% or more.

Abstract: A stacked surrounding wall capacitor (SSWC) using a modified stacked capacitor storage cell fabrication process. The SSWC is made up of polysilicon structure, having an elongated v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

Abstract: The present invention provides a programmable structure for programmable integrated circuits, such as programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digitlines as well as on the wordlines thereby providing two, one time programmable nodes at each digit/word/digit' intersection. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines, also having one-sided ozone spacers, and further overlying parallel rows' of digitlines' in a programmable read only memory. With a lower level of digitlines passing under a middle level of wordlines and an upper level of digitlines' passing over the middle level of wordlines, a row/column/digit' matrix is formed thereby providing a programmable row/column/row' matrix in a memory array.

Abstract: A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: The basic component of the output ESD protection circuit of the present invention comprises a low resistance connected in series between an output pad and conventional active output pad pullup and pulldown drivers. In a preferred embodiment, a polysilicon resistor is connected in series between an output pad and a metal bus. On the metal bus, a lateral bipolar device is connected in parallel to an n-channel pulldown at an output node and a common potential (conventionally labeled as V.sub.SS). The pullup device is also an active n-channel pullup device connected between an operating potential (conventionally labeled as V.sub.CC) and the output node. Both drains of the two n-channel devices have n-well underneath the n+ diffusion in the area where metal contacts are formed to thereby prevent metal spiking to the substrate during an ESD event. This circuitry combination provides ESD protection equal to or greater than the voltage range of +8000/-2000 V for the HBM response (the Mil. Std.

Abstract: The present invention introduces a method to fabricate a self-aligning active PMOS device fabricated on top of an NMOS active device, thereby forming a CMOS inverter having a gate electrode being common to the two active devices. This fabrication technique provides for a less expensive method to form a CMOS inverter that may be used simply as an inverter or as a building block to construct an SRAM cell which results in reduced manufacturing cost compared to that of conventional CMOS fabrication processes. Standard transistors are formed in a starting substrate with a poly gate sandwich structure having its top layer serving as the channel region of the active PMOS of the present invention. Next, an inter-poly dielectric is deposited and a buried contact are formed to allow a subsequently deposited P+ poly of the PMOS device to make connection to the substrate diffusion areas. This P+ layer of poly is planarized to clear the poly over the NMOS poly gates and exposed the underlying oxide.

Abstract: Described is a lead frame design which allows for greater control of adhesive thickness which bonds the die with the die paddle on the lead frame. A number of bumps on the surface of the lead frame contact the die, thereby keeping the die a controlled distance from the surface of the die paddle. A sufficient amount of adhesive is applied to the die paddle to ensure a minimum allowable contact of the die with the adhesive, and the adhesive with the lead frame. Enough force is applied to the surface of the die to allow contact between the die and the bumps on the surface of the inventive lead frame. The force applied to the surface of the die, therefore, has no effect on the thickness of the bond line, as long as some minimum amount of pressure is applied.

Abstract: A low cost active P-channel load for use in semiconductor devices is developed. The active P-channel load may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The P-channel load is built overlying an active NMOS device and not only takes up less die space but also allows for a simple process to construct the P-channel load. This P-channel device is easily incorporated into an SRAM process flow to build an SRAM cell made up of active NMOS devices that utilize the P-channel devices as pullups.

Abstract: The present invention provides improved programmability of antifuse elements by utilizing local enhancement of an underlying diffusion region. During an existing fabrication of a semiconductor device using antifuse elements after the access lines (usually word lines) are formed, a self-aligning trench is etched between two neighboring access lines thereby severing an underlying diffusion region. Following an etch back of the access lines' spacers a low energy, heavy dose implant dopes the exposed edges of the diffusion region resulting from the spacer etch back, as well as the bottom of the trench. An antifuse dielectric is formed followed by placing of a second conductive access line (usually the source lines) thus filling the trench to serve as the programmable antifuse element. The heavily doped areas in the diffusion region will now allow a reduction in programming voltage level, while providing a sufficient rupture of the antifuse dielectric.

Abstract: The present invention comprises a programmable structure for a integrated circuits, such as programmable read-only memory (PROM) or option selections/redundancy repair on dynamic random access memories (DRAMs), which utilizes both antifuse and fuse elements for multiple programming. Various combinations of anti-fuse and fuse elements (series or series-parallel combinations) will allow multiple programming of a given node in a particular circuit design to allow greater programming flexibility.

Abstract: A stacked multi-fingered cell (SMFC) capacitor using a modified stacked capacitor storage cell fabrication process. The (SMFC) is made up of polysilicon structure, having a multi-fingered cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: The present invention introduces an effective way to produce a thin film capacitor utilizing a high dielectric constant material for the cell dielectric through the use of a single transition metal, such as Molybdenum, for a bottom plate electrode which oxidizes to form a highly conducting oxide. Using Molybdenum, for example, will make a low resistive contact to the underlying silicon since Molybdenum reacts with silicon to form MoSix with low (<500 .mu..OMEGA.-cm) bulk resistance. In addition, Mo/MoSix is compatible with present ULSI process flow or fabricating DRAMs and the like.

Abstract: In the present invention, a stable and uniform texturized surface of a conductive structure is developed by annealing, oxidizing and etching a layer of metal silicide that has been deposited over a semiconductive material. Using this process during fabrication of memory cell in a DRAM will increase storage node capacitance by creating texturized capacitor cell plates that will retain their textured surfaces throughout implementation of conventional DRAM fabrication processes.

Abstract: A self-aligned vertical intrinsic resistance for use in semiconductor devices is developed. The self-aligned vertical intrinsic resistance may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The vertical positioning of the intrinsic resistance not only takes up less die space but also allows for a simple process to construct the resistance by eliminating a photomask step that is normally required prior to implanting an intrinsic resistance used in conventional fabrication processes.

Abstract: The present invention describes a CVD process to deposit a titanium film at a high deposition rate that has excellent uniformity and step coverage while avoiding gas phase nucleation and coating of the reactor chamber walls. The vapor of a heated liquid titanium source enters a modified, plasma enhanced, cold wall reaction chamber and is mixed with H.sub.2 as it reaches a wafer substrate surface. As the gas vapors reach the heated wafer substrate a chemical reaction of TiCl.sub.4 +2H.sub.2 .fwdarw.Ti+4HCl is triggered, thereby depositing a uniform titanium film upon the substrate surface. The deposition rate is further enhanced by the presence of rf plasma above the substrate's surface.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.

Abstract: The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.