Abstract: A quick-release multiple gas injection pipe connector fitting for removable attachment to a gas reaction chamber having a plurality of gas injection passages. The fitting permits a number of gas inlet lines to be removed from or attached to a reaction chamber fixture in one operation without a separate removal or attachment step for each gas line. The fitting also facilitates a process where the reaction gases are preferably mixed only at the reaction site and not before.

Abstract: A single-chip microcomputer comprises at least two separate and independent electrically erasable programmable read only memories (EEPROMs) on-board which may be independently programmed, erased and read. Each part of the split EEPROM has its own data bus and address bus. Programming and erasing is controlled by a program register which has separate bits for configuring and latching the data and address buses of a selected EEPROM array, for providing programming voltage to the array of choice and for choosing between programming and erasing the selected array. The split EEPROM provides versatility to the user in allowing one part of the EEPROM to be programmed while the program stored in another part of the EEPROM or RAM may be read and utilized. In addition, test time and effort of the microcomputer may be considerably reduced.

Abstract: A method for fabricating an insulated gate field effect transistor (IGFET) having a semiconductor gate with a first portion and a second portion where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon gate of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. A semiconductor material layer, such as polycrystalline silicon (polysilicon) is selectively protected by a gate pattern mask whereby the end portions of the gates are produced by the lateral diffusion of the dopant under the edges of the gate pattern mask. Thus, the technique for defining the different portions of the gate uses other than photolithographic techniques which are limited in their resolution capabilities, and thus is readily implementable in submicron device feature processes.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.

Abstract: A data processor for performing a division operation requiring shifting and the counting of the number of shifts, having no dedicated counters therefor. An additional shift left path from the temporary register of the previous bit to the next bit address bus is the only extra circuitry added, which greatly simplifies the shift left circuit of the temporary register. In addition, the dedicated counter may be eliminated as a formerly idle address incrementer circuit now performs the shift left and count functions. Not only are formerly idle registers now being used for lengthy shifting and cycle counting operations, but an overall savings in chip area is recognized, since the dedicated counter is eliminated and the dedicated shifter is greatly simplified.

Abstract: A process for removing the edge bead of films that are spun onto a planar substrate, which edge bead collects at the edge of the substrate. In processes such as the manufacture of integrated circuits, the edge bead of brittle substances such as glass, SiO.sub.2, tends to shatter upon subsequent high temperature processing and generates particles which contaminate further processing of the integrated circuits. A pulsed or repeated application of a solvent on the edge of the substrate, a backwash step of constant rotational speed and a deceleration over time provides a means of smoothing and gradual cutting back of the spun on film edge. The deceleration spin has a starting rotational speed and a final rotational speed; and the subsequent backwash step is always at a constant rotational speed lower than the starting speed of the previous deceleration spin.

Abstract: A process having three steps to etch a vertical trench with rounded top corners and rounded bottom corners. The first step involves anisotropically etching a vertical trench through an opening in a masking layer to approximately 85 to 90% of the final trench depth to give a trench with sharp or abrupt top corners and sharp bottom corners. The second step rounds the top corners and the third step extends the trench depth and provides rounded bottom corners. Using CHF.sub.3 as an etch species and adjusting the DC bias differently for each step gives better profile control and better critical dimension (CD) control.

Abstract: An isolation formation process that minimizes bird's beak encroachment and preserves gate oxide integrity in the active region. Future active areas are protected by a structure having a central protective material layer, such as a thermal oxide, surrounded by a ring of thermal nitride. The thermal nitride and central protective material are coated by active region protection masking covers. In one embodiment, the masking covers include sidewalls over the thermal nitride ring. In another embodiment, the central protective material layer is overetched beneath an undercut covering layer to provide an undercut filled by the sidewall. All of these features contribute to bird's beak encroachment prevention which may be narrowed to as little as 0.07 microns per side.

Abstract: A complementary metal-oxide-semiconductor (CMOS) isolation structure where the field isolation structure between the adjacent areas of different conductivity types has a channel stop doped with boron or phosphorus affected by germanium. The dual use of germanium and a second dopant selected from the group of phosphorus and boron provides a more precisely placed channel stop, since the germanium retards the diffusion of the boron and phosphorus and surprisingly provides improved width effect for the devices in the well where the channel stop is employed. Alternatively, the germanium may be placed in such a manner as to avoid retarding absorption of boron or phosphorus into the field oxide and retard its diffusion over the well of a different conductivity type where it is not desired.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDS) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Conformal materials such as CVD polysilicon may also be employed for this purpose. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implantation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation.

Abstract: A method for determining the etch bias of a particular semiconductor device feature layer material in a given etch process employing a hard mask reference material that changes very little or not at all during the etch under examination, and using a cross-sectional examination of the critical dimensions to determine the bias. Silicon dioxide would be a suitable hard mask material for a plasma etch bias study, for example. Preferably, a scanning electron microscope would determine the etch bias in one microphotograph. The need for optically taking two or more separate measurements to optically determine the etch bias, and the possiblility for incorporating error between measurements, is eliminated. In addition, the contribution of photoresist erosion to the etch bias of the device feature layer may be independently determined.

Abstract: A process for forming an insulated gate field effect transistor (IGFET) having a semiconductor gate with a central portion and end portions on either side thereof where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon portion of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. The central portion of the gate is formed by conventional gate patterning whereas the end portions are formed by typical procedures for forming sidewall spacers using a conformal layer of in situ doped polycrystalline silicon (polysilicon) or other semiconductor material and an anisotropic etch.

Abstract: A technique for suppressing hillock growth in metal films on integrated circuits through multiple thermal cycles by argon implantation. Although it was known that ion implantation of many species such as arsenic suppressed the growth of hillocks in metal films through one thermal cycle, it was discovered that only one of the proposed ions, argon, would suppress hillock formation for multiple subsequent thermal cycles. For the other species, hillock formation would reoccur after multiple cycles. This characteristic is important for double layer metal (DLM) processes to prevent interlayer shorting.

Abstract: A deep, buried n.sup.- channel blanket implant beneath both n.sup.- channel and p-channel devices in MOS integrated circuits, whether complementary MOS (CMOS) or not. It is known to use deep, lightly-doped n.sup.- channel implant to improve the characteristics of p-channel (PMOS) devices, although one skilled in the art would expect such an n.sup.- implant to be detrimental to n-channel (NMOS) devices. It has been discovered that such implants not only do not degrade the NMOS devices, but in fact improve their performance, with respect to body effect and junction capacitance.

Abstract: An integrated circuit test site assembly for testing pin grid array (PGA) packaged integrated circuits having removable contact pins. The removable contact pins, which are preferably spring-loaded pogo pins, enable the test site assembly to be repaired quickly and easily with a minimum of down time. In addition, the test site need only be loaded with the number of pins required to make contact with the PGA lead pattern.

Abstract: A two-device trench cell having a transistor surrounded by a capacitor. This combined capacitor and transistor cell can be used as a memory cell. The capacitor is first fabricated into the walls of a trench leaving a narrowed trench into which a vertical metal-oxide-semiconductor field-effect-transistor (MOSFET) may be fabricated. One of the plates of the capacitor doubles as a source/drain layer of the transistor.

Abstract: Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the parallelism inherent in a CAM array and by the addition of a bulk load mechanism to enable all of the word lines simultaneously. The further addition of an ALLHIT indicator to assess all of the match lines in a single operation also reduces the number of operations and simplifies the test algorithm. The ALLHIT indicator may be an AND gate or a scan path.

Abstract: An integrated circuit comprising: a semiconductor die having an integrated circuit formed therein; a package for supporting the die and for providing electrical contact thereto, the radiation properties of the package having been characterized as follows: fabricating a detector using a semiconductor fabrication technique, the detector having substantially the same dimensions as an integrated circuit to be packaged in the packaging materia; packaging the detector using integrated circuit packaging techniques; and measuring the radiation environment of the detector.

Abstract: A continuous ionizer adapted to introduce selected ions into a continually flowing stream of liquid. To ensure that a maximum concentration of ions is incorporated, the continuous ionizer is configured so that turbulent and intimate mixing of the ionizing gas and liquid to be ionized occurs. The flow of ionizing gas is regulated by a liquid level sensor to prevent a gas/liquid mixture from proceeding downstream from the ionizer. The apparatus and method of this invention are particularly suited to situations where deionized water is used in a process which causes undesired static electricity discharges, and clean, ion-possessing water is preferred, such as semiconductor processing.

Abstract: A built in self test input generator (BISTIG) for programmable logic arrays (PLAs) providing exhaustive fault coverage, but requiring additional space of only 8 to 15% of the PLA area. The BISTIG contains a test vector generator and a product term control, each of which has a sequence generator and associated decoder. The sequence generators generate log.sub.2 (N) and log.sub.2 (M) test vectors for the test vector generator and the product term control respectively, where N is the number of inputs to the PLA and M is the number of product terms connecting the first level of the PLA with the second level of the PLA.