Abstract: A timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN- voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: A method of operating a memory cell includes detecting a first power supply anomaly or condition. When the first power supply condition occurs, memory cell access to bit lines is disabled, a series of shadow memory access FETs within the memory cells are enabled and data from the memory cells are coupled to memory FETs within the memory cells to store data corresponding to the data from the memory cells in the memory FETs. The memory FETs include nanocrystals of semiconductor material in gate dielectrics of the FETs. Electrons are stored in the nanocrystals of semiconductor material to represent the data stored in the memory cell. When a second power supply condition is detected, the data stored in the memory FETs are written back to the memory cells.

Abstract: A method of fabricating a junction-isolated semiconductor device is provided which includes the following steps. Within a first P-type buried region second N-type buried regions are formed. Over the first and second buried regions, an N-type epitaxial layer defining a surface of the device is grown. In the epitaxial layer, P-type isolation regions extending from the surface down to and in electric continuity with the first buried region and defining, with the first buried region, N-type wells incorporating the second buried regions is formed. And, P-type annular border regions in the epitaxial layer and to the side of the isolation regions are formed. The steps of forming isolation regions and annular border regions semiconducting regions being performed in a single step of selectively introducing doping ions.

Abstract: A method of reducing the memory required for decompression of a compressed frame by storing frames in a compressed format using DCT compression and decoders for implementing such a method are disclosed. The decoder is coupled to a memory where the frame can be stored. The decoder includes a decoder module having a parser, a block decoder module and a motion compensation engine. The decoder module is coupled to a DCT encoder module, which has an output coupled to the memory. The decoder also includes a stored DCT decoder module, which has an input coupled to the memory, a first output coupled to the motion compensation module and a second output that functions as an output of the decoder. In operation, any prediction frames needed for motion compensation decompression of the compressed frame are decompressed in the stored DCT decoder module. The compressed frame is decompressed in the decoder module to obtain a decompressed frame.

Abstract: An integrated circuit package for direct mounting of an integrated circuit die to a printed circuit board is disclosed. The integrated circuit die includes a silicon sensor that detects changes in external variables, such as providing an image of a human fingerprint. The integrated circuit die has wire bond pads formed along only one side thereof to provide maximum exposure of the top surface area of the silicon sensor. The die is affixed to the printed circuit board and an adhesive surface coating, such as epoxy, is applied to the die and the printed circuit board for sealing the die thereto. The adhesive surface coating is formed from a first bead applied to the printed circuit board to cover at least the ends of the wires bonded to the board and a second bead applied to the first bead and the die to enclose the sides of the die and partially overlap the wire band pads and wires on top surface thereof.

Abstract: A method of a storing a picture in a memory such that bandwidth can be reduced when retrieving an array portion of the picture from the memory, and a memory architecture are disclosed. The memory is subdivided into a plurality of words for storing a picture having rows and columns. The picture is partitioned into two or more stripes each having a predetermined number of columns. The number of bytes in one row of one stripe is equal to the number of bytes in one word, for storing the data in one row of a stripe in one word. For the case of progressive video sequences or images the memory is organized in frame structure. For the case of interlaced video sequences or images, the memory is organized in field structure. For a frame picture to be stored in a frame organized memory or a field picture to be stored in a field organized memory, the data in the first row of one of the stripes is stored in a first word.

Abstract: A process for the manufacturing of an integrated circuit having DMOS-technology power devices and non-volatile memory cells provides for forming respective laterally displaced isolated semiconductor regions, electrically insulated from each other and from a common semiconductor substrate, inside which the devices will be formed; forming conductive gate regions for the DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions. Inside the isolated semiconductor regions for the DMOS-technology power devices, channel regions extending under the insulated gate regions are formed. The channel regions are formed by an implantation of a dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that the channel regions are formed directly after the implantation of the dopant without performing a thermal diffusion at a high temperature of the dopant.

Abstract: The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

Abstract: A non-volatile storage device storing a data bit received from a bitline via an accessing circuit. A coupling circuit couples either the bitline, or a complementary bitline to a biasing circuit dependent on the logic level of the data bit stored in the storage device. The biasing circuit generates a match signal when a data bit having the same logic level as the stored data bit is applied to the bitline.

Abstract: A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. The write simulation circuit includes a memory cell replicate which replicates the time required for writing data to memory cells of the array. After the memory cell replicate has changed state, a signal is output via a switching circuit to the variable timer circuit for generation of a write termination signal. The memory cells are tested at various write cycle speeds by controlling the variable timer circuit. The variable timer circuit is set to terminate the write as quickly as possible after a successful write to the memory cells has been completed.

Abstract: A layout is provided for an SRAM structure. The layout includes a first storage transistor cross-coupled to a second storage transistor to form an SRAM cell. The source regions of the first and second storage transistors are formed in a common region in the substrate to provide a more compact and dense array. The memory cell also includes a first access transistor and a second access transistor appropriately coupled to the appropriate data storage notes. The gate electrodes for the storage transistors and the access transistors are substantially parallel to each other thus providing advantages in operational characteristics and layout efficiencies. The channel regions are also exactly perpendicular to the gate electrodes and are parallel to each other for each of their respective transistors, thereby obtaining similar benefits. The memory cell is designed having a low aspect ratio, preferably lower than 1.2.

Abstract: A power down brake latch circuit for dynamically braking a spindle motor in a disk drive system is disclosed. The power down brake latch circuit includes a reservoir capacitor, a smoothing capacitor, a timing circuit, and a logic circuit. The timing circuit includes a voltage divider and a bandgap comparator. The smoothing capacitor absorbs a BEMF voltage from the spindle motor as it rotates after losing power. The timing circuit generates a first signal when a voltage on the smoothing capacitor falls below a threshold. The logic circuit brakes the spindle motor in response to the loss of power and the generation of the first signal.

Abstract: An electrically erasable and programmable non-volatile memory device comprises at least one memory sector comprising an array of memory cells arranged in rows and first-level columns, the first-level columns being grouped together in groups of first-level columns each coupled to a respective second-level column, first-level selection means for selectively coupling one first-level column for each group to the respective second-level column, second-level selection means for selecting one of the second-level columns, first direct memory access test means activatable in a first test mode for directly coupling a selected memory cell of the array to a respective output terminal of the memory device, redundancy columns of redundancy memory cells for replacing defective columns of memory cells, and a redundancy control circuit comprising defective-address storage means for storing addresses of the defective columns and activating respective redundancy columns when the defective columns are addressed.

Abstract: A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.

Abstract: The present invention relates to a device for starting and supplying a fluorescent tube, including a resonant system connected to the tube and to a rectified supply circuit with a switch in series. A first detector controls the switch to turn off when the current provided by the supply exceeds a determined threshold; and a second detector controls the switch to turn on for each transition through zero of the voltage on a node of the resonant system and for each transition through a minimum of this voltage.

Abstract: A modular integrated circuit package is mounted on a surface of a printed circuit board. The integrated circuit package includes a rigid interposer releasably coupling a component module to a substrate member designed to be affixed to the printed circuit board. The substrate member has a first side with plural first electrical connectors for connection to the circuit board and a second side with second electrical connectors coupled to the first electrical connectors. The interposer includes a plurality of electrical connectors that couple electrical connectors of the component module to the second electrical connectors of the substrate member. The component module also includes plural clip members that engage a lower surface of the interposer to releasably couple the component module to the interposer.

Abstract: A method and a circuit for switching a motor controller from pulse width modulation to linear control for a brush-less, sensor-less, poly-phase DC motor. The method includes steps of operating a drive circuit for a poly-phase direct current motor in a pulse width modulation mode and determining that a zero crossing will occur within a predetermined interval. The method also includes steps of enabling a bias current to a transconductance operational amplifier and changing an operating state of the drive circuit from the pulse width modulation mode to a linear mode. The method further includes steps of determining that the zero crossing has occurred, disabling the bias current to the transconductance operational amplifier and changing the operating state of the drive circuit from the linear mode to the pulse width modulation mode.

Abstract: A read circuit reads data stored in a memory cell that is coupled to a bit line. The read circuit includes a comparison circuit, such as a sense amplifier, having a first input terminal coupled to the bit line and having a second input terminal and a data output terminal. A switch is coupled between the bit line and the second input terminal of the comparison circuit and includes a control terminal that is coupled to receive a control signal.

Abstract: For eliminating the emphasis given an audio signal in the transmitter, an audio signal processor of an audio device (e.g., a car radio) contains a low-pass filter. In order to attenuate the spurious higher-frequency signal fractions in case of poor reception and accordingly low received field strength, the cutoff frequency of the low-pass filter is shifted in the direction of lower frequencies in accordance with a received field strength signal when the field strength becomes lower. In order to avoid external adjusting components and save pins on the IC chip, the field strength signal is supplied to an analog-to-digital converter and the latter supplies a digital signal to a low-pass filter whose cutoff frequency is variable. For this purpose the low-pass filter contains a number of integrated components one of which is connected or disconnected by a digit place of the digital signal in each case.

Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC.sub.max. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.