Abstract: A distance sensor has a capacitive element in turn having a first armature which is positioned facing a second armature whose distance is to be measured. In the case of fingerprinting, the second armature is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: Powerful nanosecond-range lasers using low repetition rate pulsed laser deposition produce numerous macroscopic size particles and droplets, which embed in thin film coatings. This problem has been addressed by lowering the pulse energy, keeping the laser intensity optional for evaporation, so that significant numbers of the macroscopic particles and droplets are no longer present in the evaporated plume. The result is deposition of evaporated plume on a substrate to form thin film of very high surface quality. Preferably, the laser pulses have a repetition rate to produce a continuous flow of evaporated material at the substrate. Pulse-range is typically picosecond and femtosecond and repetition rate kilohertz to hundreds of megahertz.

Abstract: A system and method for selecting between two biasing modes for biasing magneto resistive heads in a disk drive. A mode selector selects either a voltage biasing circuit or a current biasing circuit to supply the bias voltage or bias current, respectively, to a magneto resistive head. The selection can be based on changes in parameters in the disk drive or magneto resistive heads during disk drive operation.

Abstract: The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN− voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: A write head is described having a switchable damping resistance coupled in parallel with an inductor. The damping resistance is decoupled from the inductor by rendering a transistor nonconductive when a direction of current in the inductor changes. The damping resistance is then coupled to the inductor before oscillations begin in the current in the inductor. The decoupling of the damping resistor eliminates power dissipation in the damping resistor during a change in the direction of current in the inductor.

Abstract: A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.

Abstract: Two improved process steps of eliminating cracks within TiN and/or BPSG layers after the RTP process are provided. The first is to provide a low deposition power, preferably below 6.5 KWH, and a high process pressure, preferably above 5.6 mTorr, to the TiN layer. No crack is found for this improved TiN deposition process when the RTP temperature rises from 450° C. to about 700° C. The second is to provide a low RTP temperature, preferably below 595° C., to the semiconductor wafer. No crack, again, is found by using this low RTP temperature.

Abstract: A non-volatile memory device organized with memory cells arranged by rows and columns in a matrix structure comprising source lines for memory cell groups. A switch is set between at least two rows or columns or source lines, which has two no pilotable terminals connected respectively to each one of the two rows or columns or source lines and a pilotable terminal connected to a logic circuitry. The switch allows a precharge of one of the two rows or columns or source lines by capacitive means associated to a each one of the two rows or columns or source lines after the other of the two rows or columns or source lines is connected to a higher voltage than that of said one of the two rows or columns or source lines.

Abstract: The present invention relates to a circuit for supplying a load from an approximately D.C. voltage obtained by rectifying an A.C. voltage, including means for extracting from the rectified A.C. voltage an information depending on a phase angle variation of the A.C. voltage, and a means for making the approximately D.C. load supply voltage independent from the phase angle variation of the A.C. voltage.

Abstract: A filter reduces artifacts, such as grid noise and staircase noise, in block-coded digital images with image block boundaries. The type of filtering is determined after an estimation of the image global metrics and local metrics. For areas of the image near grid noise, the filter performs low pass filtering. For image fine details, such as edges and texture, no filtering is performed so that masking is avoided. The filter operates in intra-field mode and uses a fuzzy logic process, pixel deltas, and dual ramp generators to determine the horizontal and vertical length of a processing window surrounding an image block boundary.

Abstract: A nonvolatile memory device has a signature code generator generating a present signature code from an algorithm modified dynamically as a function of predefined varying parameters. A variable parameter may be the address of a memory cell being addressed; in this case the output of the code generator is a function of data read from the cell array, the previously calculated signature code and the address of the read data. The data are read in sequence, using an internal clock generated by an internal clock oscillator. In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code varies in dynamic way; at the end of memory scanning, the signature code is compared to an expected result.

Abstract: A redundancy UPROM cell includes at least one memory element of EPROM or Flash type, having a control terminal and a conduction terminal to be biased, an inverter register connected to the memory element by at least one MOS transistor. Such cell also includes a pass transistor which connects said conduction terminal to a data line and a pull-up transistor which connects the data line to a supply voltage reference. The UPROM cell has the great advantage to result in smaller dimensions in comparison with the cells of known type, at equal final functions and performances being assumed.

Abstract: A method and apparatus for measuring torque of a rotating shaft is provided. In one embodiment, the apparatus includes a transducer assembly that is attached to a shaft. The transducer assembly includes a first plate member, a plurality of webs extending from the first plate member and a second plate member connected to the webs. A plurality of strain gauges are mounted on the transducer assembly at selected locations and in selected patterns. As torque is applied to the shaft, the torsional load from the shaft causes stress in the first plate member, the web members, and the second plate member. The strain gauges measure this stress and generate signals that provide a measure of the stress. The signals transmitted from the sensing circuit are compared with calibration data, and the torque value is inferred.

Abstract: A circuit and method to drive an H-bridge circuit is disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, it is boosted with a circuit including a capacitor and is used to drive one of the upper transistors. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. When the logic signal is received that is the complement of the first logic signal, the other upper and lower transistors turn on, thereby driving current through the inductive head in the other direction. Since all of the transistors in the H-bridge circuit are NMOS transistors, boosted driving circuits are used to quickly change the direction of the flux through the inductive head.

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. Each task operates according to a state machine progression. The transaction interface accepts data information from the tasks and forms data packets for delivery to the 1394 bus. The data packets are initially sent via an associated hardware register, but if busy, the transaction interface polls for other available registers. In addition, all queued transactions are loaded into registers in the most expedient manner.

Abstract: For an analysis of an electrical behaviour of a specific cell of a monolithically integrated circuit, a simulation model is used which is composed of a fine model part of the cell of interest and a coarse model part of the remainder of the integrated circuit.

Abstract: A method for starting a polyphase DC motor having a rotor. The position of the rotor is detected by initiating current in each of the phases of the motor and measuring a time period between the initiation of current in the coil and an instant when the current exceeds a threshold current. The phase in which the current reaches the threshold in the shortest amount of time is the phase closest to the position of the rotor. A phase closest to the position of the rotor is identified in each of an odd number of trials, and a starting phase is selected as the phase identified in the majority of trials. The motor is started by providing current to the starting phase.

Abstract: The device described permits selection between two design options of an integrated circuit by causing a corresponding circuit unit of the integrated circuit to adopt one of two possible different operative states. It comprises an inverter, of which the output terminal is connected to the control terminal of the circuit unit and the input terminal is connected to a first supply terminal by means of a conductor which can be broken by means outside the integrated circuit, and to the second supply terminal by means of a capacitor in parallel with a diode connected for reverse conduction. The device described does not require control signals, takes up a very small area, has practically zero consumption, and can be formed in unlimited numbers on the same integrated circuit.

Abstract: A circuit assembly for an operational amplifier has an input stage with first and second input terminals and an output terminal. An output stage has a first input terminal coupled to the output terminal of the input stage, a second input terminal, and an output terminal. A feedback circuit is coupled between the output terminal of the output stage and the second input terminal of the input stage. An interconnection circuit is coupled to the first and second input terminals and the output terminal of the output stage and to a reference voltage source. The interconnection circuit has first, second, and third modes, such that the second input terminal of the output stage is coupled to the reference voltage source when the interconnection circuit is in the first mode.

Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called “smart power” type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures.