Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor.

Abstract: A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor material. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by patterning the first dielectric layer to selectively cover a portion of the substrate and leave an exposed portion of the substrate.

Abstract: The memory cell is of the type with a single level of polysilicon, and is produced in a substrate of semiconductor material with a first type of conductivity, and comprises a control gate region with a second type of conductivity, formed in the substrate in a first active region; regions of source and drain with the second type of conductivity, formed in the substrate in a second active region; and a floating gate region which extends transversely relative to the first and the second active regions. The control gate region is surrounded by a first well with the first type of conductivity, which in turn is surrounded, below and laterally, by a third well with the second type of conductivity. The regions of source and drain are accommodated in a second well with the first type of conductivity, which in turn is surrounded below and laterally by a fourth well with the second type of conductivity.

Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.

Abstract: A charge pump voltage booster circuit for generating, from a first voltage supplied at the input to the circuit, an output voltage with an absolute value that is higher than the first voltage, comprises at least one stage having a charge pass element and a charge storage capacitor with a first plate connected to an output of the charge pass element and a second plate controlled by a square-wave control signal of period varying between a reference voltage and the first voltage, supplied to the second plate of the capacitor by means of a driver circuit comprising a pull-up transistor and a pull-down transistor connected in series between the first voltage and the reference voltage. Means of overdriving at least one of the said transistors, either the pull-up transistor or the pull-down transistor, supply to the said at least one transistor a firing control voltage that has a higher absolute value than the first voltage.

Abstract: The invention concerns a wind power installation comprising a pylon, a foundation for the pylon and an energy transfer unit for transfer of the current generated to the power network. The wind power installation according to the invention is distinguished in that the weight of the energy transfer unit is carried by the foundation of the pylon of the wind power installation.

Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.

Abstract: A computer system includes an address and data path interconnecting an on-chip CPU with a module and an external communication port, event request packets being generated by the CPU and the module and memory access packets being generated by the CPU, each packet having a destination address and being distributed in parallel format on-chip with a reduction to a more serial format for off-chip communication.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide graiicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: A voice coil motor control circuit provides control signals to a voice coil motor circuit drivel that is coupled to a voice coil motor. A current sensing resistor is coupled in series with the voice coil motor. The control circuit includes a sense amplifier having inputs that couple to the current sensing resistor and includes a feedback circuit that includes an input and also includes an output that couples to the voice coil motor driver. In a first mode of operation, the feedback circuit input is coupled to an output of the sense amplifier. The control circuit also includes an inverting operational amplifier. In the first mode of operation, the inverting operational amplifier is bypassed. In a second mode of operation corresponding to deployment of a read/write head from a parked position onto the disc, the inverting operational amplifier is coupled in series between the sense amplifier output and the feedback circuit input.

Abstract: When programming, for each programming pulse, a threshold voltage whose value is increased with respect to the previous programming pulse is applied to the gate terminal of each cell to be programmed. After an initial step, the increase of threshold voltage of the cell being programmed becomes equal to the applied gate voltage increase. In order to reduce the global programming time, keeping a small variability interval of threshold voltages associated with each level, to pass from a threshold level to a following one, each cell to be programmed is supplied with a plurality of consecutive pulses without verify, until it is immediately below the voltage level to be programmed, and then a verify step is performed, followed by subsequent programming and verify steps until the cell to be programmed reaches the desired threshold value.

Abstract: An alphanumeric character image recognition system includes a first stage comprising at least a first, second and third digital image signal processing network having each at least one input terminal and at least one output terminal and said networks being designed to process image information from digital image signals, and comprising at least a first, second and third memory register having each at least one input terminal and at least one output terminal and the input terminals of the first, second and third memory registers being connected to the output terminal of the first network, the output of the second network and the output terminal of the third network respectively and said memory registers being designed to contain the image information processed by the first, second and third digital image signal processing networks, and a second stage characterized in that said second stage comprises at least one first and one second classifier network having each at least one first and one second input termina

Abstract: The distance sensor has a capacitive element (33, 34) in turn having a first plate (23) which is positioned facing a second plate (18) whose distance is to be measured. In the case of fingerprinting, the second plate is defined directly by the skin surface of the finger being printed. The sensor includes an inverting amplifier (13), between the input and output of which the capacitive element (33, 34) is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective word line switching between a first operating voltage, in turn switching at least between the supply voltage and a programming voltage higher than the supply voltage, and a second operating voltage, in turn switching at least between the ground voltage and an erase voltage lower than the ground voltage. Each biasing circuit includes a level translator circuit receiving at the input the row selection signal and supplying as output a control signal switching between the first and the second operating voltages and an output driver circuit receiving as input the control signal and supplying at the output the biasing signal.

Abstract: A system and method for reducing noise using recursive noise level estimation. The system and method for noise reduction substitute a target pixel in a processing window with a weighted average of a plurality of neighboring pixels according to the degree of similarity between the target pixel and the neighboring pixels. The similarity is based on the noise level affecting the image and the local brightness of the processing window. The filter is based on fuzzy logic and filters out noise without smoothing the image's fine details. The filter uses a human visual system (HVS) response to adjust brightness.

Abstract: A microprocessor having a logic control unit and a memory unit. The logic control unit performs execution of a number of instructions, among them being memory operation requests. A memory operation request is passed to a memory unit which begins to fulfill the memory request immediately. Simultaneously with the memory request being made, a copy of the full memory request is made and stored in a storage device within the memory unit. In addition, an identification of the request which was the origin of the memory operation is also stored. In the event the memory request is fulfilled immediately, whether it be the retrieval of data or the storing of data, the results of the memory request are provided to the microprocessor. On the other hand, in the event the memory is busy and cannot fulfill the request immediately, the memory unit performs a retry of the memory request on future memory request cycles.

Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.

Abstract: A circuit and method for scan testing some or all connections to a device, the device under test having at least one output and a plurality of inputs greater than the number of outputs. Such a device typically includes built-in self-test capability. An exclusive-OR gate receives the plurality of inputs and generates an exclusive-OR output. A multiplexer receives the at least one data output and the exclusive-OR as respect inputs, and selectively outputs one of such as a data output. Such selection of the output of the multiplexer is controlled responsive to a scan test signal, the exclusive-OR output being output from the multiplexer in a scan test.

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.