Abstract: A microelectronic device is designed such that it includes a region between electrodes having a switchable ohmic resistance wherein the region is made of a substance comprising components Ax, By, and oxygen Oz. The ohmic resistance in the region is reversibly switchable between different states by applying different voltage pulses. The different voltage pulses lead to the respective different states. An appropriate amount of dopant(s) in the substance improves the switching, whereby the microelectronic device becomes controllable and reliable.

Abstract: A system for the automated testing of software in a distributed environment. A system server includes a test bucket for storing test data. System resource availability data is maintained in the system server. Test requests submitted by a user are processed by the system server. Upon appropriate resource availability a dynamic test script is generated by the system server and sent to appropriate client machines for execution. Client processes on the client machines manage the execution of the tests. Client machines return test results to the system server for generation of a test report.

Abstract: Memory is managed by controlling the expansion of memory contents, especially in those computing environments in which the memory contents are compressed. Control is provided by imposing some restrictions to memory references outside a specified subset of the memory contents, and by controlling the transfer of items into the subset. In one example, the transfer of items into the subset is based on a function of parameters, including an estimate of the amount of free space in the memory.

Abstract: A liquid crystal display device includes a substantially transparent substrate layer between a grating layer and a pixel electrode that comprises a solid conductor and an electrically conductive mesh. The device also includes a liquid crystal layer between said pixel electrode and a substantially transparent counter electrode that is arranged at a transparent cover plate. It further includes an active circuit element layer with a field effect transistor for controlling the pixel electrode. A method for manufacturing the liquid crystal display device is further disclosed wherein the pixel electrode is formed by printing a patterned substance onto the substrate layer and selectively plating a conductor onto said substance. The device may also comprise a conductor mesh comprising rows of conductor lines crossing with columns of conductor lines, wherein at least part of the conductor lines are randomly spaced from each other.

Abstract: A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.

Abstract: An image display apparatus with a display device for displaying images and a viewing device for viewing an image in the left eye and a different image in the right eye. Two smaller images, a left image and a right image, are created from the same two-dimensional image. The left image includes, as it's left most part, the left most part of the two-dimensional image, the right image includes, as it's right most, the right most part of the image two-dimensional image, and both the left and right images include a common central part of the full image. When the left and right images are displayed such that the left eye sees one image and the right eye sees the other image, the viewer sees the two-dimensional image as a virtual image that can be wider than the viewable width of the display device. The width of the virtual image can be varied to accommodate the viewer.

Abstract: A method and structure for a “dynamic CCR/sparse directory implementation,” includes maintaining state information of the main memory cached in the shared caches of the other compute nodes, organizing a cache directory so that the state information can be stored in a first area efficient CCR directory format, switching to a second sparse directory format if the entry is shared by more than one other compute node, and dynamically switching between formats so as to maximize the number of entries stored in the directory.

Abstract: Scheme for processing an input signal A(t) by N resonators (17), each having parameters characterizing it, to generate N individual output signals. Then each of the N individual output signals is weighted using a corresponding weight to generate N individual weighted output signals which are superposed to obtain M output signals C(t). One of the parameters or the weight depend on a time signal P(t).

Abstract: The present invention provides an apparatus, method, and system for determining a time of arrival (TOA) and time differences of arrival (TDOA) of a transmitted signal {S} receivable at different locations of known spatial coordinates. The system comprises a first transmitter 10 with a respective antenna feed point positioned at an a priori unknown location P and emitting a first signal {S}. The system includes furthermore a set of transceivers or transponder units 20, 30 comprising first receivers 22, 32 for receiving first signals {S} by means of respective antennas with feed points located at known locations Ln. Such system also comprises second transmitters 26, 36 emitting respective derived second signals {{tilde over (S)}n} after known and scheduled respective time intervals &dgr;n as measurable between the feed points of said respective first receiving antennas located at known locations Ln and respective second transmitting antenna located at locations L′n.

Abstract: An active matrix display device has an inspection circuit for inspecting the image quality. The inspection circuit includes a plurality of input terminals for inputting a test signal and a plurality of test transistors connected respectively to the input terminals. Input test signals which are to be sent to sub pixel sections from the individual input terminals are controlled by the associated test transistors to display a desired test screen. The test transistors are preferably amorphous silicon TFTs.

Abstract: The method and circuits of the present invention aim to associate a norm to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. The set of norms, referred to as the “component” norms is memorized in specific memorization means in the ANN. In a first embodiment, the ANN is provided with a global memory, common for all the neurons of the ANN, that memorizes all the component norms. For each component of the input pattern, all the neurons perform the elementary (or partial) distance calculation with the corresponding prototype components stored therein during the distance evaluation process using the associated component norm. The distance elementary calculations are then combined using a “distance” norm to determine the final distance between the input pattern and the prototypes stored in the neurons.

Abstract: A liquid crystal display comprises an input for inputting a video signal from a host and a storage medium for storing the previous brightness level of the video signal input through the input. A determinator is provided for determining an output brightness level based on the previous brightness level stored in the storage medium and the next brightness level of the next video signal input to the input, so as to make the time integration quantity of a brightness change substantially equal to an ideal quantity of light in a stationary state with respect to the next brightness level. Further included are drivers for driving an image displaying liquid crystal cell based on the output brightness level determined by the determinator.

Abstract: A display apparatus is characterized by having a display panel for displaying an image, a light source for supplying light to the display panel, and a flat-surface lighting surface member which has a lighting surface emitting light, radiated from the light source, as flat-surface light while being arranged with the display panel. A housing contains the display panel, the light source, and the flat-surface lighting surface member. The housing further includes a window through light passes the flat-surface lighting surface member and leaks to the outside.

Abstract: A compressed memory system includes a cache, and compressed memory including fixed size storage blocks for storing both compressed data segments and fixed size storage blocks defining a virtual uncompressed cache (VUC) for storing uncompressed data segments to enable reduced data access latency. The compressed memory system implements a system and method for controlling the size of the VUC so as to optimize system performance in a manner which permits the avoidance of operating system intervention which is required in certain circumstances for correct system operation. The system solves-these problems by implementing one or more thresholds, which may be set by the operating system, but which, after being sets control the size of the VUC independently of the operating system or other system software.

Abstract: A method and structure for reducing access latency and contention in a processing system is disclosed. The invention detects when the amount of available memory is outside a prescribed range, and responsively selects data blocks for compression (to add to the available memory,) or decompression (to use surplus available memory for uncompressed data,) until the amount of available memory is within the prescribed range. When data blocks are compressed, a DOC is determined and stored as an attribute in the directory entry associated with the data block. A most recently used list of recent data block addresses prevents those, as well those data blocks with poor DOC attributes, from being selected for recompression. All zero data blocks are detected to avoid standard compression/decompression overhead.

Abstract: An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank.

Abstract: An illuminating-light controller includes a light modulator for projecting light on a corresponding area by tilting a reflecting surface. A first light source emits a first light that is projected on the corresponding area by illuminating the first light to the reflecting surface of the spatial light modulator being tilted at a first angle. A second light source for emits a second light that is projected on the corresponding area by illuminating the second light to the reflecting surface of the light modulator being tilted at a second angle. Still further, included is a control section for controlling the first light emitted from the first light source and the second light emitted from said second light source.

Abstract: A discrete pattern, formed by dots discretely arranged in two dimensions, is provided wherein the dots included in a rectangular area having a longitudinal length of Lx and a transverse length of Ly satisfy expression (1), D≦0.13N−1 15  (1) (in expression (1), N denotes the number of dots included in a predetermined area, and D is obtained by expression (2), wherein A(x,y) defines the number of dots, of a total of N dots, included in a rectangular area for which a line segment extended from reference coordinates (0,0) to an arbitrary coordinate point (x,y) is a diagonal line), [Ex.

Abstract: A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this (146,130) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.

Abstract: The present invention is directed to a microprocessor (MPU) 10 comprising a bridge chip 12 including a bus retry output part (40) for outputting a bus retry (BRTY) signal; a bus retry detection part (30) for determining whether a bus retry signal is input from the bridge chip 12; and a bus cycle controller (38) for suspending a currently executed bus cycle in response to detection of the bus retry signal and for re-starting the suspended bus cycle. The bridge chip also preferably includes an interrupt detection part (32) for determining whether another process request is issued during suspension of the bus cycle; and an interrupt controller (38) for executing that other process before re-starting the suspended bus cycle.