Abstract: A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device.

Abstract: A method for operating a fluorescent lamp which is connected to a series resonant circuit with a resonant circuit inductance and a resonant circuit capacitance. The method includes applying an excitation AC voltage at an excitation frequency to the series resonant circuit using a half bridge circuit, which has an output to which the series resonant circuit is coupled, and which has a first and a second switch which are alternately switched on and off on the basis of a frequency signal. A current flowing through the resonant circuit is monitored for the presence of a critical operating state. The switched-on times of the first and second switches are shortened in comparison to switched-on times which are predetermined by the frequency signal, upon detection of a critical operating state.

Abstract: A semiconductor device having a topology adjustment and a method for adjusting the topology of a semiconductor device. The semiconductor device includes a semiconductor wafer having first and second opposing sides with an active area formed on a first portion of the first side having a topology extending a first distance above the first side. A support member is attached to a second portion of the first side and extending a second distance above the first side, wherein the first distance is about the same as the second distance. In some exemplary embodiments, the support member is formed by applying adhesive to the second portion. The wafer is then spun to adjust the second distance.

Abstract: A semiconductor device has a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type complementary to the first conductivity type arranged in or on the first semiconductor layer. The semiconductor device has a region of the first conductivity type arranged in the second semiconductor layer. A first electrode contacts the region of the first conductivity type and the second semiconductor layer. A trench extends into the first semiconductor layer, and a voltage dependent short circuit diverter structure has a highly-doped diverter region of the second conductivity type. This diverter region is arranged via an end of a channel region and coupled to a diode arranged in the trench.

Abstract: A tire position identification system and method include a transmitter that is configured to send an initiation signal. A receiver is configured to receive the initiation signal and attenuate the initiation signal until the initiation signal is within a first predetermined range of a reference signal. A controller identifies the position of a tire in response to the attenuation. In some embodiments, the reference signal is adjusted until the attenuated initiation signal is within a second predetermined range of the adjusted reference signal, and the position of the tire is identified further in response to the amount of adjustment of the reference signal.

Abstract: A charge compensation component having a drift path between two electrodes, an electrode and a counterelectrode, and methods for producing the same. The drift path has drift zones of a first conduction type and charge compensation zones of a complementary conduction type with respect to the first conduction type. A drift path layer doping comprising the volume integral of the doping locations of a horizontal drift path layer of the vertically extending drift path including the drift zone regions and charge compensation zone regions arranged in the drift path layer is greater in the vicinity of the electrodes than in the direction of the center of the drift path.

Abstract: A chip carrier includes first, second and third layers with the second layer situated between the first and third layers. The first and third layers are formed of a first material and the second layer is formed of a second material. The second layer has a plurality of holes extending therethrough and the first material fills the holes.

Abstract: A circuit including Hall plates and an amplifier. The Hall plates are configured to provide Hall voltages in a homogenous magnetic field such that a first Hall plate has a first positive voltage and a first negative voltage and a second Hall plate has a second positive voltage and a second negative voltage. The amplifier is configured to receive the Hall voltages and provide a first output voltage that corresponds to the first positive voltage and the second positive voltage and a second output voltage that corresponds to the first negative voltage and the second negative voltage.

Abstract: A semiconductor device including a chip including an integrated circuit, a conductive layer, a copolymer layer and metal elements. The conductive layer is disposed over the chip and electrically coupled to the integrated circuit. The copolymer is disposed on the conductive layer. The metal elements are electrically coupled to the conductive layer via through-connects in the copolymer layer.

Abstract: The semiconductor device has a semiconductor body with a semiconductor device structure. The semiconductor device structure has a first electrode, a second electrode and a gate electrode. The gate electrode is designed to form a conductive channel region. An insulating layer at least partially surrounds the gate electrode. A semi-insulating layer is provided between the gate electrode and at least one of the first electrode and the second electrode. The semi-insulating layer is located outside the conductive channel region and has an interface state density which is greater than the quotient of the breakdown charge and the band gap of the material of the semiconductor body.

Abstract: A semiconductor device including a wafer-level LED includes a semiconductor structure coupled to first and second electrodes. The semiconductor includes a P-doped portion of a first layer to an N-doped portion of a second layer. The first layer includes a surface configured to emit light. The first electrode is electrically coupled to the P-doped portion of the first layer on a first side of the semiconductor structure. The first side is adjacent to the surface that is configured to emit the light. The second electrode is electrically coupled to the N-doped portion of the second layer on a second side of the semiconductor structure. The second side is also adjacent to the surface that configured to emit light.

Abstract: A constant temperature hot-conductor anemometer includes a set of electrically conductive pins including a pair of inner pins and a pair of outer pins. A conductor is electrically and mechanically coupled to the pins. A current source is coupled to the inner pins. The current source is configured to provide a current through the conductor between the inner pins. A voltage sensor is coupled to the outer pins and configured to measure a voltage across the conductor between the outer pins. The current source and voltage sensor are configured to maintain a constant resistance of the conductor between the inner pins. In an example, a second set of pins, a second conductor and a second circuit are also used to measure dynamic temperature of a fluid and also to calibrate resistances at a known ambient temperature.

Abstract: An integrated circuit device comprises a first semiconductor chip on a first substrate and a second semiconductor chip on a second substrate. A side surface of the first semiconductor chip is facing a side surface of the second semiconductor chip. At least one electric cable is provided to be connecting the first substrate to the second substrate.

Abstract: An integrated circuit including an array of memory cells, a circuit, volatile storage, and non-volatile storage. The circuit is configured to detect defective memory cells in the array of memory cells and provide addresses of the defective memory cells. The volatile storage is configured to store the addresses, where each entry in the volatile storage includes one of the addresses and a volatile storage master bit. The non-volatile storage is configured to store the addresses, where each entry in the non-volatile storage includes one of the addresses and a non-volatile storage master bit.

Abstract: A semiconductor device has a semiconductor body with a semiconductor device structure including at least a first electrode and a second electrode. Between the two electrodes, a drift region is arranged, the drift region including charge compensation zones and drift zones arranged substantially parallel to one another. At least one charge carrier storage region which is at least partially free of charge compensation zones is arranged in the semiconductor body.

Abstract: A support with solder ball elements for loading substrates with ball contacts is disclosed. One embodiment provides a system for loading substrates with ball contacts and a method for loading substrates with ball contacts. The support has a layer of adhesive applied on one side, the layer of adhesive losing its adhesive force to the greatest extent when irradiated. The support has solder ball elements, which are arranged closely packed in rows and columns on the layer of adhesive in a prescribed pitch for a semiconductor chip or a semiconductor component.

Abstract: A semiconductor device includes a singulated semiconductor package having a leadframe, a chip electrically coupled to the leadframe, encapsulating material covering the chip and a portion of the leadframe, and a material layer disposed over opposing ends of the leadframe. The leadframe includes a first face and an opposing second face, the first and second faces extending between opposing ends of the leadframe, where the second face configured to electrically couple with a circuit board. The chip is electrically coupled to the first face. The encapsulating material covers the chip and the first face of the leadframe. The material layer is configured to improve solderability of the singulated semiconductor package to the circuit board.

Abstract: A method of manufacturing a semiconductor device. The method includes providing a semiconductor chip including contact elements on a first face and a first layer between the first face and a second face opposite the first face. Placing the semiconductor chip on a carrier with the contact elements facing the carrier and etching the semiconductor chip until the first layer is reached.

Abstract: A method of manufacturing a semiconductor device. The method includes providing a wafer having a first face and a second face opposite the first face, selectively doping the wafer via the first face to selectively form etch stop regions in the wafer and etching the wafer at the second face to the etch stop regions.

Abstract: A semiconductor device with a semiconductor body and to a method for producing it. In one embodiment, the semiconductor body has first electrodes which contact first highly doped semiconductor zones and complementary-conduction body zones surrounding the first semiconductor zones. The semiconductor body has a second electrode which contacts a second highly doped semiconductor zone. Between the second semiconductor zone and the body zones, a drift zone is arranged. Control electrodes which are insulated from the semiconductor body by a gate oxide and act on the body zones for controlling the semiconductor device are arranged on the semiconductor body. The body zones have minority charge carrier injector zones with complementary conduction to the body zones, arranged between the first semiconductor zones and the drift zone.