Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.
Type:
Grant
Filed:
May 20, 2004
Date of Patent:
June 19, 2007
Assignee:
Infineon Technologies AG
Inventors:
Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba
Abstract: A device and method is described for the frequency division of an input clock signal, in which from the input clock signal at least two output clock signals are generated, with an output pulse frequency equal to an input pulse frequency divided by a given factor, whereby with a phase detector a phase difference is measured between the at least two output signals and each of the at least two output clock signals is either inverted or not inverted, as a function of the phase difference determined. A method of this type is particularly suitable for the demultiplexing of an input data signal, and can also be designed to be multi-step.
Abstract: A stored-value card assembly comprises a stored-value card and a magnetic sheet. The stored-value card defines a first surface and a second surface opposite the first surface. The first surface includes an account identifier linking the stored-value card to at least one of a financial account or a financial record. The stored-value card is substantially non-magnetic. The magnetic sheet is placed on the second surface of stored-value card and is removably coupled to the stored-value card. Methods of assembling a stored-value card assembly, methods of encouraging purchase and facilitating use of a stored-value card assembly, and other embodiments are also disclosed.
Abstract: The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor.
Type:
Grant
Filed:
July 1, 2002
Date of Patent:
March 13, 2007
Assignee:
Infineon Technologies AG
Inventors:
Jessica Hartwich, Johannes Kretz, Richard Johannes Luyken, Wolfgang Rösner
Abstract: In order to generate an output signal delayed compared to an input signal and with a defined mark-to-space ratio, it is useful to produce at least first and second intermediate signals delayed differently with respect to the input signal and to combine them to form the output signal so that a rising (or negative) edge of the first intermediate signal determines a rising edge of the output signal, and a rising (or negative) edge of the second intermediate signal determines a falling edge of the output signal. In particular a plurality of successive versions of an input timing signal delayed by an equal amount can be generated with a mark-to-space ratio of 50%.
Abstract: A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.
Abstract: A random access memory comprises a plurality of data pads and an array of memory cells comprising a first portion of memory cells and a second portion of memory cells. The random access memory comprises a first line configured to receive first data signals between the first portion of memory cells and the data pads and a second line configured to receive second data signals between the second portion of memory cells and the data pads. The first portion of memory cells is configured to be made inaccessible to eliminate the first data signals and a first number of the data pads and the second portion of memory cells is configured to be made inaccessible to eliminate the second data signals and a second number of the data pads.
Type:
Grant
Filed:
December 4, 2003
Date of Patent:
October 18, 2005
Assignee:
Infineon Technologies North America Corp.
Abstract: A personal surveillance system configured to be worn by an individual includes a communication system configured to record communication files, a locating system configured to determine a location of the personal surveillance system, and a transmitter configured to send the communication files and the location of the personal surveillance system to a remote monitoring station. The locating system includes a satellite system interface configured to determine the location of the personal surveillance system and an alternate positioning system configured to determine the location of the personal surveillance system in at least one situation where the satellite system interface cannot determine the location of the personal surveillance system.
Abstract: A reluctance drive includes a stator, a phase winding (16) on the stator, a rotor (12) that is movable relative to the stator, a controller for applying a current to the phase winding (13), and a sensor for measuring the phase current in the winding (16). Aspects of the invention detect when the phase current has passed its peak, compute when the peak phase current occurred using information on when the phase current passed its peak, determine rotor position using the computed position of the peak phase current.
Abstract: A method of baking bread from dough including the steps of preparing the dough, rolling out the dough into a flat strip in the range of approximately 1-30 mm, cutting the strip of dough into pieces, baking the flat pieces of dough in an oven for a short time (in the range of approximately 2-8 minutes) at a temperature in the range of approximately 250-270° C. and cooling and, if desired, packaging the flat pieces of baked bread. The method of the present invention saves a great deal of time, energy and labor, and results in an attractive product. The invention also includes the resultant bread and a cutting means for use with the method.