Abstract: A security protocol that dynamically implements enhanced mount security of a filesystem when access to sensitive files on a networked filesystem is requested. When the user of a client system attempts to access a specially-tagged sensitive file, the server hosting the filesystem executes a software code that terminates the current mount and re-configures the server ports to accept a re-mount from the client via a more secure port. The server re-configured server port is provided the IP address of the client and matches the IP address during the re-mount operation. The switch to a secure mount is completed in a seamless manner so that authorized users are allowed to access sensitive files without bogging down the server with costly encryption and other resource-intensive security features. No significant delay is experienced by the user, while the sensitive file is shielded from un-authorized capture during transmission to the client system.

Abstract: A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree.

Abstract: A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability solver, and in response to determining that the verifying step has hit the composite target, a counterexample to is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample, and a second abstraction is built by composing the refinement pairs. One or more learned clauses and one or more invariants to the second abstraction and the second abstraction is chosen as the current abstraction. The current abstraction is verified with the satisfiability solver.

Abstract: A wireless communication device, a method, and a computer program product that enable multiple subscriber numbers to be concurrently assigned to and supported within a single communication device, such as a wireless/cellular phone. The communication device is designed with circuit components and logic that allows two or more subscriber numbers to be concurrently programmed into the device. Each subscriber number is individually supported, with the logic also providing some overlapping functionality. A user selectively utilizes one of the subscriber numbers to originate a new call out and/or accept an incoming call to that subscriber number and may toggle between subscriber numbers to communicate on.

Abstract: According to a method of simulation processing, one or more HDL source files describing a digital design including a plurality of hierarchically arranged design entities are received. The one or more HDL source files include one or more statements instantiating a plurality of print events within the plurality of hierarchically arranged design entities, where each print event has an associated message and at least one associated signal in the digital design. The one or more HDL source files are processed to obtain a simulation executable model including a data structure describing the plurality of print events defined for the simulation executable model and associating each of the plurality of print events with its respective associated signal.

Abstract: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.

Abstract: Forms data is reusable in a first webpage after a user goes to a second webpage, and then returns to the first webpage. After providing access to a first webpage via a portal User Interface (UI) on a display on a client computer, a data entry input of forms data for the first webpage is received from a user of the client computer. The user is then provided access to a second webpage via the portal UI. In response to providing access to the second webpage, the server stores the forms data. In response to the user inputting a request to return to the first webpage from the second webpage, the server creates a populated first webpage by populating the first webpage with the multiple forms data that is stored in the server, and then returns the populated first webpage to the portal UI.

Abstract: A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.

Abstract: A technique of operating a wireless communication device includes selecting, from a primary sequence group that includes respective primary sequences, one of the respective primary sequences as a first portion of a cell identification (ID). In this case, the respective primary sequences are each associated with respective secondary sequence subgroups included in a secondary sequence group. Each of the respective secondary sequence subgroups include secondary sequences. One of the secondary sequences is selected (from one of the respective secondary sequence subgroups that is associated with the selected one of the respective primary sequences) for a second portion of the cell ID. At least some of the secondary sequences are only included in one of the respective secondary sequence subgroups. The first portion of the cell ID is encoded on a first downlink waveform that is to be transmitted and the second portion of the cell ID is encoded on a second downlink waveform that is to be transmitted.

Abstract: A data flow control method and system within a data switch. The data switch includes a plurality of input sections each having an associated input buffer and each transmitting data to an output section. In response to a detection of congestion within the output section, data transmissions from the plurality of input sections to the output section are paused. Input buffer occupancies of each of the input sections are then determined. Thereafter, and in response to a backpressure relief signal, the restart of said data transmission from each of the input sections to the output section is delayed in inverse proportion to each of the determined input buffer occupancies.

Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.

Abstract: A method, system and computer program product for providing an integrated environment for processing business object documents (BODs). The integrated environment utilizes an IntelliBod system to employ standard business semantics while adapting modified business terms. Applications requesting integration, or mapping, map to common business semantics of the BODs, and the IntelliBOD system manages the business semantic (and technical) integration of the applications. IntelliBOD systems utilize JAVA environments to process requests, thereby reducing cost and space required to maintain general purpose middleware.

Abstract: A method of data processing that converts a set of restricted terms, which is considered prohibited for use in source files, into an encrypted form, which prevents unauthorized users from reading the set of restricted terms. Further, the terms from a selected source file are encrypted with the same algorithm that was used on the set of prohibited terms. Then, a determination is made if the selected source file has one or more of the encrypted, restricted terms. In response to determining that the selected source file has one or more of the encrypted, restricted terms, an indication is given that the selected source file has one or more of the encrypted, restricted terms.

Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

Abstract: A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors. In one embodiment, a first test pattern and a second test pattern are applied to a set of hardware bit positions. The first and second patterns are multiple logic level patterns and the second test pattern is the logical complement of the first test pattern. The first and second test patterns are utilized by the ECC logic to detect correctable errors having n or fewer bits. One or more bit positions of a first correctable error occurring responsive to applying the first test pattern are determined and one or more bit positions of a second correctable error occurring responsive to applying the second test pattern are determined. The determined bit positions of the first and second correctable errors are processed to identify a multiple-bit error within the set of hardware bit positions.

Abstract: An apparatus for providing management storage via a USB port of a computer system is disclosed. The apparatus includes a flash memory, a first and second switches, a first and second inverters, a designated port, and a controller. Coupled to the flash memory, the first and second switches are controlled by a main power of a computer system in a complementary manner. The first and second inverters, which are powered by a standby power of the computer system, are coupled to a respective control input of the first and second switches. The designated port, which is coupled to the flash memory via the first switch, allows data to be read from and written to the flash memory without booting up the computer system. On the other hand, the controller, which is coupled to the flash memory via the second switch, allows data to be read from and written to the flash memory by the computer system only after the computer system has been booted up.

Abstract: In a software partition (SWPAR) environment, a method, system and computer program product enables a SWPAR to be remotely booted, independent of the booting of the OS on the global system environment, using network file system (NFS) services and protocols. A request to mount a NFS, hosted by an external server into a SWPAR environment is transmitted. The NFS services are automatically transitioning to a first operating state that enables support for user-level NFS services without requiring the NFS services be active. The SWPAR is automatically booted and access to the SWPAR provided during operation of the NFS services in the first operating state. Once the SWPAR has completed booting, the NFS services is transitioned back to a normal operating state in which SWPAR operates as a standalone device providing its own user-level NFS services.

Abstract: A method, system and computer program product for implementing general purpose PCRs with extended semantics (referred to herein as “ePCRs”) in a trusted, measured software module. The module is designed to run in one of a hypervisor context, an isolated partition, or under other isolated configurations. Because the software module is provided using trusted (measured) code, the software implementing the PCRs is able to run as a simple software process in the operating system (OS), as long as the software is first measured and logged. The software-implemented ePCRs are generated as needed to record specific measurements of the software and hardware elements on which an application depends, and the ePCRs are able to ignore other non-dependencies.

Abstract: A method for automatically detecting and correcting one or more hang conditions within one or more of a master device and target device of a serial bus interface when one or more signals are held in an invalid state. A hang timer monitors one or more operations of the serial bus when the serial bus is participating in a serial bus transfer. If the transfer does not end before the bus timeout value has been exceeded, the hang timer will issue a reset to the state machine forcing the state machine back to an idle state. The hang timer will also disable the serial bus drivers of the state machine, whereby the hang condition is corrected.

Abstract: A method for managing shared passwords on a multi-user computer system is disclosed. A set of shared passwords and an administrator internal key are initially generated. After the receipt of an administrator external key, the administrator internal key is encrypted with the administrator external key. For each user level within the computer system, an internal key is generated by hashing the administrator internal key. For each user level within the computer system, each of the shared passwords encrypted with a respective one of the internal keys. The internal keys and the encrypted shared passwords are then stored in a non-volatile storage device.