Abstract: A method within a data processing system in which a processor handles conflicts, which occur during performance by an asynchronous memory mover of an asynchronous memory move (AMM) operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation by which the actual data is moved from a source to a destination memory location, independent of the processor. The memory mover sets a flag bit to indicate that the asynchronous memory mover is currently performing an AMM operation at the memory. When the processor receives a memory access operation, the processor checks the value of the flag bit before issuing the new memory access operation, and checks the associated address of the AMM operation to determine possible address conflicts. The processor then evaluates and responds to address conflicts to prevent corruption of data during an AMM operation.

Abstract: A optical disc drive is disclosed. The optical disc drive includes a housing and a tray configured to accommodate a disc therein. The optical disc drive also includes an automatic return-type eject switch, a drive controller, and an eject controller. Mounted in the housing, the automatic return-type eject switch is configured to generate an eject signal. In response to the eject signal, the drive controller ejects the tray. In response to the eject signal, the eject controller supplies an electric power to the optical disc drive, and transmits a pseudo eject signal to the drive controller to eject the tray by way of a line through which the eject signal has been transferred after a predetermined time period from the supply of the electric power has lapsed.

Abstract: A battery pack is disclosed. The battery pack includes a battery, an impact sensor, a processor and a memory. The impact sensor is capable of generating an impact signal in response to a detection of an impact on the battery pack. The processor is capable of generating impact information based on the impact signal, and processor continues to count a number of charging times to the battery after the generation of the impact information. The memory is capable of storing the impact information and the number of charging times. The processor can refer to the memory to deliver a control command to a battery charger so that the battery can only be charged up to an allowable charge capacity smaller than a full charge capacity after an occurrence of an impact when the battery pack is attached to the battery charger. The charging to the battery stops when the number of the counted charging times reaches a predetermined number of allowable charging times that is allowed after the generation of the impact information.

Abstract: A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.

Abstract: A mobile device includes first identification circuitry and second identification circuitry. The first identification circuitry is associated with a first network and the second identification circuitry is associated with a second network. The mobile device simultaneously registers itself with the first and second networks using the first and second identification circuitry, respectively. The first and second identification circuitry may each comprise subscriber identity modules. The mobile devices handle outgoing and incoming calls based on user preferences. The user may override the preferences for selected calls.

Abstract: In accordance with the present invention, a storage area is provided within a particular home for storing food-related items. A database of intended food-related inventory items for the storage area is adjusted by a controller according to food-related inventory preferences received at the controller. The controller updates the database of intended food-related inventory items according to inputs from a monitoring device that monitors the addition and removal of food-related items within the storage area. A communication medium coupled to the controller transmits a selection of items from among the database of intended inventory items that are absent from the storage area.

Abstract: A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a system call to request allocation of backing storage in physical memory for global shared memory accessible to all of the multiple tasks within the parallel job, where the global shared memory is in a global address space defined by a range of effective addresses. Each task among the multiple tasks receives an indication that the allocation requested by the system call was successful only if the global address space for that task was previously reserved and backing storage for the global shared memory has not already been allocated.

Abstract: A method, system, and computer program product for timing the execution of code to facilitate the debugging of a Korn shell script. A user specifies the starting point and stopping point of a block of code by placing a time-code function at the beginning and end of the block of code. Furthermore, the user specifies a threshold value within the time-code function that corresponds to a maximum amount of time allotted for execution. The user defines a label variable to identify the output. When the block of code is executed, the time-code function calculates the time of execution and outputs the results. If the code contains an error that causes the execution time to exceed the threshold value, the time-code function halts the execution of the block of code and an error message is displayed. The error message then assists the user in debugging the block of code.

Abstract: A design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and the simulation includes counting occurrences of the count event in the count event counter to obtain a count event value. A threshold is also established for an aggregate count event value for the count event counter. After completion of the testcase, a determination is made whether addition of the count event value to the aggregate count event value for the count event counter would cause the aggregate count event value to exceed the threshold. If not, the count event value is recorded in a testcase data storage area, and the count event value is accumulated in the aggregate count event value. If so, the count event value is discarded without recording the count event value in the testcase data storage area.

Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.

Abstract: A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a respective system call to request reservation, without allocation of backing storage in physical memory, of a global address space defined by a range of effective addresses as global shared memory accessible to all of the multiple tasks within the parallel job. At least two of the tasks within the parallel job allocate global address spaces including a same effective address.

Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.

Abstract: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.

Abstract: While an asynchronous memory move (AMM) operation is ongoing, a prefetch request for data from the source effective address or the destination effective address triggers cache injection by the AMM mover of relevant data from the stream of data being moved in the physical memory. The memory controller forwards the first prefetched line to the prefetch engine and L1 cache, the next cache lines in the sequence of data to the L2 cache, and a subsequent set of cache lines to the L3 cache. The memory controller then forwards the remaining data to the destination memory location. Quick access to prefetch data is enabled by buffering the stream of data in the upper caches rather than placing all the moved data within the memory. Also, the memory controller places moved data into only a subset of the available cache lines of the upper level cache.

Abstract: A system and methods (300, 400) are disclosed for conserving energy in a multimode communication device (106). A system that incorporates teachings of the present disclosure may include, for example, a communication device having a multimode wireless transceiver (202) for accessing a plurality of wireless access technologies (103), and a controller (214) for managing operations of the multimode wireless transceiver. The controller is programmed to enable (300) scanning for a select one of the wireless access technologies when the communication device is near a known location of a wireless access point. An embodiment for a network management system (100) is also disclosed.

Abstract: A method of tracking a status of a catalytic process in a mixture incorporates the use of Radio Frequency Identification (RFID) tags that have corrosive-sensitive coatings. The coatings are removable, by a corrosive in the mixture, at a rate that tracks with the rate at which a catalytic-driven process progresses. As coatings on the RFID tags are removed by the corrosive in the mixture, the digital signatures returned by the RFID tags change, in response to the corrosive damaging the RFID tags. By quantifying the number of damaged RFID tags, a determination can be made as to the progress status of the catalytic process.

Abstract: A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment.

Abstract: A method and device enables data communication via optical pulses from a light source of an electronic device. A data transfer interface is provided to support processing of selected data by a processor of the electronic device. The electronic device comprises an illumination light source, which is selectively utilized for illuminating a component in the electronic device and for transmitting data via optical pulses. An optical receiver also receives optically transmitted data. The transmission and receiving of the data is provided on a bidirectional duplex communication link created with a second optical receiver and an optical data transmission mechanism of a second electronic device.

Abstract: A read reference circuit for a sense amplifier within a chalcogenide memory device is disclosed. The read reference circuit provides a reference voltage level to the sense amplifier for distinguishing between a logical “0” state and a logical “1” state within a chalcogenide memory cell. In conjunction with a precharge circuit, the read reference circuit generates a selectable read reference current to the sense amplifier in order to detect the logical state of the chalcogenide memory cell. The precharge circuit precharges the bitlines of the chalcogenide memory cell before the sense amplifier detects the logical state of the chalcogenide memory cell.

Abstract: A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.