Abstract: One embodiment may take the form of a system for reducing the appearance of optical effects in a display. The system may include an enclosure with a first surface and a second surface. Furthermore, the system may include spacers that may be deposited on the bottom face of the first surface and/or the top face of the second surface, where the first surface may be a touch panel and/or cover lens and the second surface may be a display module. The spacers may be deposited in one layer with an anti-reflection coating. The thickness of the coating may be less than the diameter of the spacers.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: A head unit has a supply tank provided above a plurality of heads, for storing ink and a collecting part having an internal space into which ink flows from the plurality of heads. In the head unit, a plurality of ink inlet pipes serving as a plurality of passages leading from the supply tank to the plurality of heads have the same shape and the same resistance and a plurality of ink outlet pipes serving as a plurality of passages from the plurality of heads to the collecting part have the same shape and the same resistance. This equalizes respective flow rates of ink and respective pressures of ink at nozzles in the plurality of heads. As a result, it is possible to suppress variation in landing positions and the like of ink with respect to the nozzles among the plurality of heads.

Abstract: The present invention is method and apparatus for music performance and composition. More specifically, the present invention is an interactive music apparatus comprising actuating a signal that is transmitted to a processing computer that transmits output signals to a speaker that emits sound and an output component that performs an action. Further, the present invention is also a method of music performance and composition. Additionally, the present invention is an interactive wireless music apparatus comprising actuating an event originating on a remote wireless device. The transmitted event received by a processing host computer implements the proper handling of the event.

Abstract: The present disclosure generally relates to a touch-sensitive LED display device with a number of shared circuits having measurement circuitry electrically coupled to display circuitry. A processor receives signals from the measurement circuitry and may compare the signals to determine a location of the touch on the touch screen.

Abstract: Techniques are generally described related to a multi-core processor with a plurality of processor cores and a cache memory shared by at least some of the processor cores. The multi-core processor can be configured for separately allocating a respective level of cache memory associativity to each of the processing cores.

Abstract: According to exemplary embodiments of the present disclosure, a monitoring device can be provided that facilitates a supervisor in a contact center to recognize the status of each operator easily, and to recognize an irregularity in operation quickly. For example, a server can be connected to a telephone switchboard and a terminal which can include a display unit that, via a communication line; can receive operational status data indicating an operating status of a telephone from the telephone switchboard, measure an elapsed time after a change in the operational status, read out the configuration data associated and stored beforehand according to the received operational status data, generate display data for displaying an image indicating the operational status and the elapsed time, at a prescribed position on the display unit corresponding to a seating position of the operator, based on the configuration data and the elapsed time, and transmit the data to the terminal.

Abstract: A latch assembly for connection of conduit, the assembly comprising a female portion and a male portion, wherein each of the female portion and the male portion have a shell and a connection device. The connection device of the female portion includes a connection assembly with a molded-in slot, a release button, and a raised rib or alternatively is a connection opening. The connection device of the male portion includes a cantilevered region with a ramped engagement feature or alternatively is a raised cantilevered release button. When connected the cantilevered region or button deflects to accommodate the female portion until the ramped engagement feature or button engages the molded-in slot or connection opening, thus releasing the deflection. Depressing the release button disengages the latch allowing separation of the assembly.

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.

Abstract: A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Abstract: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal.

Abstract: A high dynamic range scenographic image and video projection system and method involving the projection of an image of an object or collection of objects onto the object, 2D or 3D, in such a manner than projected image elements are positioned substantially on the actual image of the object. The projection enhances or otherwise alters the hue, contrast, brightness, saturation, luminance, and/or other visible features of the object. Visual and not-visual features may be projected onto the object or the area around the object to enhance or disguise the object as well as the surroundings of the object.

Abstract: A communication system comprising a master unit and a plurality of slave units. In error mode, e.g. when a path error or a complete failure of a subscriber occurs, data transmission is carried out in a loop, starting from the master unit, via a first communication path and a second communication path.

Abstract: A method of performing money transfer send transactions begins with receiving registration information from a customer, including customer identification and qualification information and payment source identification and performing verification of at least a portion of the identification and qualification information and the payment source identification and upon sufficient verification building a distribution profile. The method proceeds by receiving from the customer and storing in the distribution profile send transaction specifications for staging each of one or more proposed send transactions, and receiving a send initiation instruction with associated customer authentication data and responsive thereto identifying a distribution profile and at least one send transaction specification to be executed.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.