Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions. One of these partitions may be a read-only partition that is normally accessible only for read accesses. However, it may sometimes be necessary to update or supplement the data stored in the read-only partition. This is accomplished by a host issuing an appropriate command to the storage device, which may be accompanied by an identifier for an appropriate level of authorization. The controller then changes the attribute of the read-only partition from “read-only” to “read/write” to allow data to be written to the partition. Upon completion, the controller changes the attribute of the partition back to read-only.

Abstract: Embodiments for validating protected data paths for digital rights management of digital objects are disclosed. Some embodiments disclosed herein may comprise processes or apparatus for transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, and/or further transfer and/or for transferring data from the computers or digital data processing systems to the peripherals. Some embodiments disclosed herein may comprise processes or apparatus for interconnecting or communicating between two or more components connected to an interconnection medium within a single computer or digital data processing system.

Abstract: Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a memory further includes repair logic coupled to the programmable elements and configured to identify programmable elements available for programming to map memory addresses to respective redundant memory. One method for remapping a memory address of a memory to redundant memory includes receiving at least a portion of a memory address to be remapped to redundant memory, determining whether a programmable element associated with the redundant memory is available for programming, and when a programmable element is available, programming the programmable element such that the memory address will be mapped to the associated redundant memory.

Abstract: Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.

Abstract: Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

Abstract: Method and apparatus according to an exemplary embodiment of the present invention can be provided. For example, first data associated with a first signal received from at least one region of at least one sample can be provided based on a first modality, and second data associated with a second signal received from the at least one sample can be provided based on a second modality which is different from the first modality. Third data associated with a reference can be received. Further data can be generated based on the first, second and third data. In addition, third data associated with a second signal received from the at least one sample can be obtained. Each of the third data can be based on a further modality which is different from the first modality and the second modality, and the further data can be further determined based on the third data. Further, the first modality can be a spectral-encoded modality, and the second modality can be a non-spectral-encoding modality.

Abstract: Embodiments of archival storage system are disclosed. The archival storage system includes one or more removable disk drives that provide random access and are readily expandable. In embodiments, some or all of the data within the removable disk drive(s) is immutable. The archiving system creates a designation for the data representing the data as having Write Once Read Many (WORM) protection. Actions associated with the data may be received and determined to be read accesses. If the actions are something other than a read access, the archiving system, in embodiments, prevents the action on the data.

Abstract: A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The protection system is used to prevent at least some of a plurality of processors in a system from accessing addresses designated by one of the processors as a protected memory address. Until the processor releases the protection, only the designating processor can access the memory device at the protected address. If the memory device contains a cache memory, the protection system can alternatively or additionally be used to protect cache memory addresses.

Abstract: A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more embodiments, a flash memory device that includes a memory cell array, a data register, a state machine, input/output pads, a row decoder, and a column decoder. The memory cell array includes a pre-charge unit that is placed between a plurality of memory cell arrays. The pre-charge unit pre-charges a bit line in a read operation. A data register is separated from the pre-charge unit and is located away from the arrays. Write data are coupled from a data register to the arrays, and read data are coupled from the arrays to the data register.

Abstract: Thermochromic filters are constructed using absorptive, reflective, or fluorescent dyes, molecules, polymers, particles, rods, or other orientation-dependent colorants that have their orientation, order, or director influenced by carrier materials, which are themselves influenced by temperature. These order-influencing carrier materials include thermotropic liquid crystals, which provide orientation to dyes and polymers in a Guest-Host system in the liquid-crystalline state at lower temperatures, but do not provide such order in the isotropic state at higher temperatures. The varying degree to which the absorptive, reflective, or fluorescent particles interact with light in the two states can be exploited to make many varieties of thermochromic filters. Thermochromic filters can control the flow of light and radiant heat through selective reflection, transmission, absorption, and/or re-emission.

Abstract: Method for finding the probability density function type and the variance properties of the noise component N of a raw signal S of a machine or a system, said raw signal S being combined of a pure signal component P and said noise component N, the method comprising: (a) defining a window within said raw signal; (b) recording the raw signal S; (c) numerically differentiating the raw signal S within the range of said window at least a number of times m to obtain an m order differentiated signal; (d) finding a histogram that best fits the m order differentiated signal; (e) finding a probability density function type that fits the distribution of the histogram; (f) determining the variance of the histogram, said histogram variance being essentially the m order variance ?2(m) of the noise component N; and (g) knowing the histogram distribution type, and the m order variance ?2(m) of the histogram, transforming the m order variance ?2(m) to the zero order variance ?2(0), ?2(0) being the variance of the pdf of the n

Abstract: A computer-implemented system and method for administering a drug registry database generates a display of a plurality of new drug/comparator drug pairings, wherein each new drug is added to the database when a threshold number of healthcare claims for the new drug have been received. Upon receiving a selection of a new drug/comparator drug pairing, and filter parameters input by a user, an analysis engine searches the healthcare claims stored in the database to identify a first and second group of patients satisfying the filter parameters input by the user; wherein the first group includes patients with claim data indicating use of the new drug and the second group includes patients with claim data indicating use of the comparator drug.

Abstract: According to the invention, a first executable environment is provided. The first executable environment is for execution within an operating system environment of a host computer system. The first executable environment is not an emulator for emulating any of another processor and another operating system. A software application is provided for installation and execution within the operating system environment. The software application is for fixed installation and not for installation in a portable fashion for being ported from one host computer system to another. The software application is then installed within the first executable environment, the installed software application installed within a removable peripheral memory storage device for execution within the first executable environment.

Abstract: The present disclosure relates to an example of a method for a first router to adaptively determine status within a network. The network may include the first router, a second router and a third router. The method for the first router may comprise determining status information regarding the second router located in the network, and transmitting the status information to the third router located in the network. The second router and the third router may be indirectly coupled to one another.

Abstract: There are provided systems, devices and methods for operating a light source to match a white point of ambient light. In one embodiment, a light control system is provided. The light control system includes a light source and a light sensor. The light sensor is configured to operate in conjunction with the light source to provide a visual effect. A controller is electrically coupled to the light source and the light sensor and configured to determine the intensity and color of light to which the light sensor is exposed and dynamically adjust the output of the light source to match the determined intensity and color of light to which the light sensor is exposed.

Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.

Abstract: Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received.

Abstract: Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.

Abstract: A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first select signal and by at least one second select signal generated by a decoder, these columns being associated with at least one program load PL controlled by a logic circuit and suitable for applying a programming pulse to a plurality of cells belonging to the enabled bit-lines, comprising a plurality of discharge transistors, each associated with a corresponding column controlled by a control signal complementary to the control signal of the adjacent discharge transistor.