Abstract: The degree of variation in the normalized site attenuation of an RF test chamber may be reduced by adjusting the properties of the RF absorbers lining the walls of the RF test chamber such that for the frequencies of greatest variation the ground screen formed by the conductive floor of the chamber appears to be much greater than its actual finite size. This may be done by progressively reducing the degree of chamber wall absorption (for the frequencies of interest) for locations on the walls closer to the floor. The reduction begins at a height above the floor equal to the height of the device under test above the floor, and proceeds to some maximum reduction in absorption at the level of the floor. The reduction in absorption has the effect of making the ground screen appear to be much larger than it really is, and may be obtained either by spacing the absorbing tiles apart by increasing amounts nearer to the floor, or by using less absorptive tiles closer to the floor, or both.

Abstract: A shortened ground path for the shield of a shielded modular connector (e.g., RJ-45, etc.) mounted against a bracket that is to be seated against a slot in a chassis is provided by a metallic grounding clip that slips over the bracket. The clip has edges that have been folded to slidably engage the bracket, and an orifice shaped to match the opening of the modular jack, so that the modular plug may pass through that orifice as it mates with the jack. The clip also has two opposing curved metal contacts along the perimeter of the orifice that engage and bear against the exposed shield portion of the modular plug as it mates with the modular jack. A pair of metal tabs engage the opening of the modular jack to align, or register, the orifice in the clip with the opening of the jack, and prevent the clip from easily sliding along the bracket once registration has been achieved.

Abstract: A bipolar negative resistance UHF oscillator having a voltage tunable resonator in its emitter circuit is operated at a fixed collector bias current and an RF detector is used as a convenient way to determine the RF current at which the oscillator is operating, by sensing the amplitude of the oscillator's output RF voltage across a constant load. An integrating error amplifier referenced to a desired detector output level responds to the actual detector output level to control the collector bias voltage for the oscillator and maintain the output of the oscillator at a fixed amplitude. Since the collector bias current is fixed, this keeps the operating point at fixed relation with respect to emitter cutoff. That relationship is chosen to be "just below" by initial selection of the constant collector bias current and the reference voltage used by the integrating error amplifier.

Abstract: Unwanted RF emissions from an imperfect enclosure surrounding an electronic apparatus are reduced by first investigating the RF field strengths inside the enclosure while the apparatus is in operation, and identifying locations where the field strengths are significantly higher than elsewhere. The field strengths at these identified locations are then lowered significantly by placing lossy materials thereat to absorb and thus dissipate RF energy. If the lossy materials are placed in the near field of the actual circuitry that generates the RF then some of that RF is dissipated according to the degree of loading, but without associated reflected energy, and without the need for the lossy material to be a free field absorber that matches the characteristic impedance of the interior of the enclosure. A hybrid arrangement also exists where the lossy material is neither a free field absorber nor located in the near field of the generator, so long as it is located in the near field of a reflector.

Abstract: Improved and less complicated leading bit anticipation (LBA) for a PKG floating point adder of n-bit 2's complement operands is accomplished by representing de-normalized (n+1)-bit operands as (n+1)-many PKG symbols. These are grouped into (n-1)-many triples, each of which has two adjacent PKG symbols in common with its neighboring triple. Presuming the existence of a least significant PKG symbol of K allows the formation of an additional triple of lesser significance. Each triple produces an associated transition bit that when set indicates, for the partial summation segment of the raw sum of bit location corresponding to the location of the triple, if the left-most two bits of the corresponding partial summation segment are, or would be with a carry-in, of opposite bit values. The bit position of the most-significant set transition bit is determined in terms of how many bit positions J that is from the most significant transition bit position.

Abstract: A circuit that finds m mod n may be obtained by creating the trial differences m-n, m-2n, m-3n, m-4n . . . , up to a limit determined by the sizes of m and n. The trial differences thus produced are examined in the order given to find the last one thereof that is non-negative. This examination involves only sign bits and a priority encoder. The magnitude portions of the various trial differences are applied as inputs to a first MUX whose selection is controlled by the priority encoder. The trial difference selected by the first MUX is applied as an input to a second MUX, whose other inputs are m itself, and zero. A separate initial comparison is performed between m and n, and controls what appears at the output of the second MUX. If n>m then the value of m appears at the output of the second MUX; if n=m or n=1 then zero appears; otherwise, m >n and it is the output from the first MUX that appears as the output of the second MUX. The output of the second MUX is m mod n.

Abstract: Extra hardware to compute the fifth vertex of a bow-tie quadrilateral is avoided by using the clipping system to do the calculations. This is accomplished by inspecting quadrilaterals (as they are projected onto the viewing plane) to see if they contain pairs of self-intersecting sides. Those that do are further classified as to type and subtype, depending respectively upon how the vertex numbering scheme identifies the intersecting non-adjacent sides and upon which of X and Y is the major axis. The hardware normally associated with a clipper can be "borrowed" and used in a non-clipping fashion to find the X coordinate for a YZ work plane (or the Y coordinate for an XZ work plane) that is associated with the fifth vertex (V.sub.4) created by the self-intersection. Once this is done the hardware of the clipper can be further borrowed to actually intersect (i.e., clip) one of the self-intersecting sides with that work plane, which produces a complete description of all the pixel coordinates for V.sub.4. Once V.

Abstract: A unified bi-directional LFSR is fabricated from latches having dual (Forward and Reverse) inputs. Each such latch accepts its inputs upon receipt of a clock signal that is respectively associated with the forward or reverse direction. The appropriate collection of XOR gates exists between latch outputs and the inputs associated with a forward clock signal, so as to produce the forward sequence. Likewise, another appropriate collection of XOR gates exists between the latch outputs and the inputs associated with the reverse clock signal. To produce a "reverse" LFSR corresponding to the polynomial that is the reciprocal of the polynomial for the "forward" LFSR, the latches of the reciprocal (reverse direction) LFSR are construed as being numbered in the opposite order. That is, a single set of latches (register) has both a forward linear feedback network and a reverse linear feedback network.

Abstract: A triangle primitive to be clipped against a viewing volume is clipped six times; once against each plane of the viewing volume. During each such clipping operation phantom vertices are discovered and the hardware vertex locations they occupy are made available for re-use. The discovery of phantom vertices is accomplished by three rules. Rule #1 is: If a previous vertex in the vertex list is outside the clip limits and is not the starting vertex, then that previous vertex's location in the vertex list can be re-used. Rule #2 is: If the current vertex in the vertex list is outside the clip limits and is the starting vertex, then the location in the vertex list containing the data for that starting vertex can be re-used to contain the intersection of that last edge and the clipping plane.

Abstract: A hardware graphics accelerator accepts lists of polygon vertices from an application environment running application and systems graphics software. After a polygon is rotated and translated as needed, it is checked for trivial accept/reject against the clip limits of the viewing volume, but is not otherwise clipped. Polygons that are not rejected are decomposed into triangles before any other operations on them are performed. After decomposition the triangles are illuminated by light sources, if desired and then clipped by a triangle clipper, rasterized, and the results sent to a frame buffer for display. The triangle clipper incorporates trivial accept/reject operation, and is capable of operating on non-planar quadrilaterals. It avoids ugly artifacts during certain clip operations when the diagonal used to decompose a quadrilateral into triangles intersects a clip plane not parallel to the viewing axis.

Abstract: A monitor passively observes traffic on a bus connecting a computer with a block-oriented mass storage device, such as a disc. The monitor parses the traffic on the bus to identify read and write operations and the bus address/block address they are intended for. The monitor creates an original confidence indicator for writes, which it then stores in a memory of its own. The memory location at which the original confidence indicator is stored is defined by a data structure indexed by the bus address/block address combination. When at a later time that same bus address/block address is read from, the monitor creates a comparison confidence indicator from data being sent from the block-oriented mass storage device to the computer, retrieves the corresponding original confidence indicator from the data structure in its memory, and compares the two. If they do not match there has been data corruption and an appropriate indication is issued to the bus or the computer.

Abstract: High speed power supply transients are suppressed in a system having fast edges and where a radial transmission line exists between the power supply and ground planes, by terminating the edges of the PCB in it characteristic impedance. In practice, this means approximating a continuous construct with many spaced instances of a discrete resistance. The dissipative terminations themselves are resistive, and if placed directly between the power supply and ground would needlessly dissipate a great deal of DC power. To prevent that they are AC coupled with a high quality coupling capacitor of sufficient capacitance to allow the resulting impedance to appear predominately resistive at and above the lowest frequency of interest, say, 100 MHz. Because of the confused nature of the reflection that may be generated at arbitrary locations within the interior of the PCB, there may well be "hot spots" within that interior that would benefit from the placement of a selected AC coupled load at or near such a spot.

Abstract: A probe for making electrical connections to the legs of an already mounted integrated circuit carries rows of tapered wedges. The wedges within a row are spaced apart by an amount that corresponds to the width of the IC's legs. For n-many legs on a side of the IC there are n+1 corresponding wedges, which then have n-many intervening spaces. As the positioned probe is pressed down the spaces between the wedges receive the legs of the IC, and wedges become wedged between the IC's legs. Each wedge has left and right conductive surfaces separated by an insulator. Each leg of the IC has a wedge to its left and a wedge to its right. Within the probe the right-hand conductive surface of the wedge to the left of a leg, and the left-hand conductive surface of the wedge to the right of that leg, are electrically connected together. Thus, the probe makes electrical contact to each leg in two places. The tapered wedges are of Ni- and Au-plated BeCu separated by acrylic adhesive and Kapton.

Abstract: An IQ modulator incorporates a quadrature network that is responsive to a frequency dependent control signal and that has in-phase and quadrature signals that are of equal amplitude and in exact quadrature over a wide range of applied frequencies. The quadrature network includes RC and CR phase shifters whose C's are fixed capacitors of equal value and whose R's are made equal to each other and to the capacitive reactance of the C's by the action of the frequency dependent control signal. The R's may be FET's. The frequency dependent control signal may be generated without express knowledge of the applied frequency by a servo loop that nulls out the amplitude difference between the in-phase and quadrature outputs from the quadrature network; it may also be generated from a look-up table as an express function of frequency. The frequency dependent control signal is split into separate instances that are applied to each R, and an offset may be introduced therebetween to provide extreme precision.

Abstract: A scan line generator for area fill of a polygon defined by a left edge and a right edge includes a Bresenham-like mechanism in a left edge machine for selecting pixels to represent a left edge by determining, for each scan line, which pixel is either on the edge or immediately to the right thereof. A right edge machine contains an identical mechanism, which also does "to-the-right-of". Both edge machines operate in the first through fourth octants, and a coordination mechanism steps the two edge machines a scan line at a time, independent of the major and minor axis of each edge. When the pixel addresses for each edge's intersection with the next scan line are found their difference along the X axis is obtained to produce the length of a fill vector on that scan line. The intersection produced for the left edge is taken as the starting point of the fill vector. Left and right edges must initially start on the same scan line, but need not be of the same length in the Y axis.

Abstract: A wide band (20 MHz to 2 GHz) four way RF power splitter/combiner is fabricated from four lengths of hard line mounted on a printed circuit board. Slots in the board allow for ferrite sleeves, and allow the hard line to be mounted right next to the surface(s) of the board. The pieces of hard line do not cross each other, and do not pass from one side of the board to the other. Two of the pieces are on one side of the board, while the other two are on the other. Within one pair the two pieces of hard line lie essentially along a straight line. Within the other pair the two pieces are offset, parallel and overlap slightly. All four pieces are parallel. Of the four pieces, one pair may be preformed to be two identical parts; the other pair may be also, although one pair may have a longer portion of center conductor extending beyond a 90.degree. bend. All four pieces of hard line are straight (i.e., their outer shields are straight, and are not bent).

Abstract: The effects of differential heating inside the calorimetric bridge are reduced by first heating the bridge externally and controlling the resulting temperature. The bridge is also heated internally by an amount that varies according to the applied power to be measured. This acts to eliminate the principal source of thermal gradients in the first instance. By applying this heat as a common mode input signal to the two terminating loads of the calorimetric bridge the bridge itself does not become unbalanced, and therefore does not attempt to measure that common power. Actual input power to be measured does initially unbalance the bridge, and is still measured as usual. A constant power circuit is response to the indication of measured power and acts to keep the sum of measured power (plus the equal amount of feedback power that balances the bridge) and the common mode power at a constant value corresponding to a full scale measurement.

Abstract: An economical, wide range and accurate power measurement technique switches an RF detector between an applied RF IN to be measured and a COMPARISON RF IN, to thus develop a difference signal. The difference signal is filtered, amplified by a logarithmic amplifier, and then converted into a DC error signal by a synchronous detector operating in step with the switching of the RF detector. The DC error signal is applied to an integrator whose output is a loop control signal. Assuming a square law detector, the square of the loop control signal is linearly proportional to the applied RF IN once a servo loop is hulled by making COMPARISON RF IN equal to RF IN. The desired power measurement is performed by digitizing the loop control signal and performing the appropriate arithmetic operations thereon. The loop control signal is also applied to an analog multiplier, where it combines with an internal RF reference signal to produce, at the output of an attenuator following the multiplier, the COMPARISON RF SIGNAL.

Abstract: An IQ modulator incorporates a quadrature network that is responsive to a frequency dependent control signal and that has in-phase and quadrature signals that are of equal amplitude and in exact quadrature over a wide range of applied frequencies. The quadrature network includes RC and CR phase shifters whose C's are fixed capacitors of equal value and whose R's are made equal to each other and to the capacitive reactance of the C's by the action of the frequency dependent control signal. The R's may be FET's. The frequency dependent control signal may be generated without express knowledge of the applied frequency by a servo loop that nulls out the amplitude difference between the in-phase and quadrature outputs from the quadrature network; it may also be generated from a look-up table as an express function of frequency. The frequency dependent control signal is split into separate instances that are applied to each R, and an offset may be introduced therebetween to provide extreme precision.

Abstract: Within an integrated circuit a source of digital data is coupled to a distant destination by a serial data path that is characterized by being either an imperfect and lossy transmission line or as possessing significant high frequency attenuation. A single phase clock accompanies the data over the serial data path. A single phase to three phase clock generator at the destination creates the three phase clock. If the destination is a shift register, then the three phase clock can be used for stage-to-stage clocking within the shift register, as well as for getting data into the input bit of the shift register.