Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window.

Abstract: A radio paging network transmits non-paging data, such as facsimile images, to lap top computer receivers by formatting the data into a series of packets and interleaving these packets, on a space available basis, into the paging signal.

Abstract: An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU. The ALU provides a variety of arithmetic and logic functions for application to 24-bit operands, but also includes a capability of manipulating such operands in accordance with sign extended opcodes without actually physically executing a sign extend operation within the microprocessor. In this manner, the ALU executes the necessary logic functions to provide the same ultimate result as sign bit extension, but does not require a separate sign bit extension step within the microprocessor to convert signed byte operand into a signed word operand.

Abstract: The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e.

Abstract: A paging system using synchronized transmission protocol and pagers active during monitor intervals to receive data transmitted during corresponding message intervals is provided with adaptive on-off radio receiver control for reducing monitor interval duration to conserve battery power. The adaptive on-off control is a function of recent timing errors and thereby accounts for environmental conditions.

Abstract: A wristwatch paging receiver is provided with an antenna matching network that automatically retunes the network at the beginning of a listening interval. During the retuning operation, a control signal is applied to a variable tuning element in the matching network, such as a varactor diode, and is swept from a minimum value to a maximum value. This sweeping is desirably performed in discrete voltage steps that correspond to unit increments of varactor capacitance. A feedback signal from the receiver, such as an AGC signal, is monitored during this operation to note which varactor bias signal yields the maximum AGC signal. After the sweep is concluded, the apparatus applies to the varactor the bias voltage that yielded the maximum AGC signal during the sweeping operation. This bias voltage is maintained through the end of the listening interval. At the beginning of the next listening interval, the process may be repeated.

Abstract: Bit synchronization is achieved by identifying potential bit sample points and assigning corresponding weight values as a function of signal noise vulnerability. The greater the possibility of error due to signal noise, the smaller the assigned weight value. The bit sample points associated with the largest accumulated weight value are taken as the appropriate data sample points for extracting information from the data signal. For a duobinary signal, zero crossings are identified as potential bit sample points and assigned a weight value corresponding to signal slope thereat. The number of possible bit sample points associated with each actual bit sample point is limited to a finite set by phase locking the carrier signal to the data rate.

Abstract: The present invention provides a microprocessor with a special OEM mode of operation that can be used by an OEM system integrator to implement special tasks such as power management. The OEM mode provided by the present invention is designed for use by a system integrator who integrates a microprocessor into a larger system such as a personal computer. The OEM mode of operation provided by this invention adds features to the overall system; however, it is transparent to system programmers. The system integrator can use the OEM mode to configure a system so that the system has certain special power management features, which can not be accessed by programmers who use the system. The OEM mode provided by the present invention is accessed by a signal on a special I-O pin. For example, an external timer can periodically provide signals to this special pin, thereby periodically interrupting the microprocessor and putting the microprocessor in the OEM mode.

Abstract: A method for searching for a station carrying paging data without unduly draining the paging receiver battery. If a station to which the receiver is presently tuned becomes unreliable, the pager scans among channels listed in a local channel list. If no paging data is received on these channels, the scanning among the local list channels may optionally proceed for a further interval at a slower rate. After it appears that paging data will not be found on channels listed in the local list, the pager begins a full spectrum search at a slow rate until it again finds a channel carrying paging data. By this arrangement, battery power is expended at a rate roughly in accordance with the likelihood of finding a paging station.

Abstract: The present invention provides an antenna or preselector tuning method and circuit that tunes an antenna or preselector in a very short period of time. The circuit of the present invention does not rely on measuring the magnitude of the signal strength at the output of the receiver as do many prior art antenna tuning techniques. With the present invention a radio frequency (RF) oscillator set to the desired receiver frequency generates an excitation signal which is lightly coupled to the antenna tuned circuit through a network. A phase detector then compares the phase of signal established in the antenna tuned circuit with the phase of the excitation signal to produce an "error" signal indicative of the phase shift of the excitation signal as it passes through the network. Using this "error" signal and locked loop (PLL) techniques, an antenna tuning voltage is created that results in a zero phase shift through the network.

Abstract: A radio receiver for use with a time slot paging system which receives intermittent data includes a direct coupled zero IF receiver circuit with at least one automatic gain control (AGC) amplifier stage. DC offset errors are removed from the AGC amplifier stages by a timed zero adjustment circuit that is switched into the AGC circuit just prior to the receipt of data. The resulting zero IF circuit may be miniaturized in monolithic form making it ideal for use in a wristwatch sized pager.

Abstract: An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU. The ALU provides a variety of arithmetic and logic functions for application to 24-bit operands, but also includes a capability of manipulating such operands in accordance with sign extended opcodes without actually physically executing a sign extend operation within the microprocessor. In this manner, the ALU executes the necessary logic functions to provide the same ultimate result as sign bit extension, but does not require a separate sign bit extension step within the microprocessor to convert signed byte operand into a signed word operand.

Abstract: An AFC switch circuit is controlled by an select input logic signal for providing a selected output signal to control the local oscillator in a miniature FM receiver. The output signal has a voltage equal to either an AFC signal voltage for AFC operation of the receiver, or a reference voltage for synthesized operation of the receiver. The AFC switch circuitry employs bipolar transistors in current mirror configurations to minimize voltage offset and to enhance isolation between the unselected input and the output while operating on a power supply voltage less than 3 volts.

Abstract: Data flow control is achieved by use of variable length flags delimiting information packets whereby longer flags result in less information flow and shorter flags result in greater information flow. A single channel carries message data as well as status and command data in information packets delimited by the variable length flags. The channel runs continuously such as to provide a constant flow of status and command data, yet includes flow control for preventing overflow and underflow of message data at the receiving end of the channel.

Abstract: Real time synchronization of radio signal data is achieved by a feedback loop between a clearinghouse generating data and a radio station transmitting data. Transmission time is adjusted in response to detected timing errors by selectively inserting padding data between certain data packets to shift data packet position within a data stream transmitted at a predetermined transmission rate. Data flow control is achieved by use of variable length flags delimiting data packets whereby longer flags result in less data flow and shorter flags result in greater data flow.

Abstract: A frequency agile data receiver checks are needed, according to a first protocol, among a plurality of channels to find a channel carrying data. A control activated by the user interrupts this first protocol and institutes a second protocol different than the first. Applied to a paging receiver, the first protocol may sequentially tune the receiver to a plurality of previously identified channels to locate a channel on which paging data is satisfactorily received. The second protocol may sequentially tune to all possible channels to locate such a channel. By this arrangement, a person who knowingly moves to a new locality (e.g., flies to another city) can instruct the paging receiver to abandon a previously identified list of candidate channels and to begin a spectrum-wide scan to locate a new satisfactory paging channels.

Abstract: A page receiver is provided a list of alternative paging channels to which it can tune if the paging channel presently being received becomes unreliable. This list, and other lists used by paging receivers in the other geographical areas, are disseminated by linked paging transmitters that broadcast identical paging signals throughtout a large geographical area. When a paging receiver finds a channel carrying paging data, it identifies which of the plurality of transmitted lists is appropriate for its use by finding the list that references the channel to which the receiver is presently tuned. The channels referenced in the identified list are then stored in a memory and may be tuned if the existing paging signal is lost. Data is desirably transmitted with the local channel lists to permit each paging receiver to locate the list relevant to its geographical area without examining each of the transmitted lists.

Abstract: A paging system where messages are numbered before they are transmitted. The paging receivers in the system compare both the number and the text information in each message which is received to the message number and the text information in the most recently received previous message. The comparison is used to determine if the same message was previously received and if the any messages were missed. The receiver includes an icon which is turned on to indicate if a message has been received. The icon is set to a blinking state if a message is received and if there is a break is the sequence of message numbers indicating that a message has been missed.

Abstract: The present invention provides a pager system which integrates a plurality of transmitters which operate at different frequencies. Some of the transmitters transmit paging messages using FM subcarrier signals (termed FM-SCA signals) and some transmit messages using a modulated carrier (termed RCC signals). The receiver includes two front ends. One front end receives and demodulates FM-SCA signals and one front end receives and demodulates RCC signals. Each paging message is transmitted on both FM-SCA transmitters and on RCC transmitters. The signals on each of the transmitters are slightly off set in time. When an assigned time slot occurs, one receiver turns on and attempts to receive a message, if it does not receive an appropriate signal, it tunes to another station that is in a stored list of stations. If the next station has an RCC flag associated therewith the RCC receiver rather than the FM-SCA receiver is operated. The entire process is controlled by a microprocessor which is a part of the system.

Abstract: The present invention provides a system which has a first computer (herein termed the SUPPORT PC) and second remotely located computer (herein termed the CUSTOMER PC). The SUPPORT PC and the CUSTOMER PC each have a display. The image displayed on the CUSTOMER PC's display is transmitted to and duplicated on the SUPPORT PC's display. The SUPPORT PC is equipped with an analog input device (such as a mouse), the efficient operation of which requires immediate visual feedback. Signals from the input device are transmitted to the remote CUSTOMER PC. The images which appear on the display of the remote CUSTOMER PC are transmitted, relatively slowly, to the display of the SUPPORT PC. In order to provide immediate visual feedback to the operator of the input device at the SUPPORT PC, a Dynamic Temporary Dual Cursor is shown on the screen of the SUPPORT PC along with the regular cursor which is transmitted from the CUSTOMER PC.