Abstract: A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal.

Abstract: A low-pressure energy system is provided that includes a combustion chamber immersed in water within an insulated container. Low-pressure air flow is introduced into one end of the combustion chamber. Fuel, sparks and water are also introduced to the combustion chamber, thereby generating steam and heat. The steam is blown through the combustion chamber to a first radiator, which emits heat and a steam exhaust, which can be used to increase the humidity of the enclosure housing the energy system. The heat generated by the combustion chamber heats the water in the insulated container. The heated water is pumped through a second radiator, thereby extracting additional heat from the system. A fan may be configured to introduce air flow over both the first and second radiators, thereby further improving heat transfer to the ambient air. Water can optionally be omitted from the combustion chamber.

Abstract: A non-volatile memory (NVM) array including a plurality of 2-bit NVM transistors arranged in a plurality of rows extending along a first axis, and a plurality of columns extending along a second axis, perpendicular to the first axis. The non-volatile memory array includes a plurality of field isolation regions located in a semiconductor substrate and a plurality of word lines extending over the semiconductor substrate along the first axis, wherein the word lines form control gates of the 2-bit NVM transistors. Oxide-nitride-oxide (ONO) structures are formed between the substrate and the word lines, wherein the nitride layer provides floating gate storage for the NVM transistors. A plurality of H-shaped source/drain regions are defined by the field isolation regions and the word lines, wherein each source/drain region serves as a source/drain for four different NVM transistors in the array.

Abstract: A VDD power-up detection circuit is provided having a p-channel transistor having a source coupled to a VDD voltage supply terminal and a gate coupled to a ground supply terminal. A first resistor or a diode element is coupled between the drain of the p-channel transistor and the ground supply terminal. An n-channel transistor has a source coupled to the ground supply terminal and a gate coupled to the drain of the p-channel transistor. A second resistor is coupled between a drain of the n-channel transistor and the VDD voltage supply terminal. A trigger circuit is coupled to the drain of the n-channel transistor. As the VDD supply voltage increases during power-up, the p-channel and n-channel transistors are both turned on. At this time, the trigger circuit asserts a control signal that enables an associated circuit to operate in response to the VDD supply voltage.

Abstract: Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to perform external accesses during one portion of a clock cycle, and required refresh operations during another portion of the same clock cycle.

Abstract: A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

Abstract: A memory redundancy scheme is provided for re-routing data signal paths to disconnect defective memory blocks in a memory array. Each memory block is provided with a corresponding routing unit. Each routing unit is coupled to its corresponding memory block and at least one additional adjacent memory block. The routing units are configured to route data between functional memory blocks and a data bus. The routing units are controlled by configuration values stored in a shifter circuit, which extends through the routing units. To replace a defective memory block, the address of the defective memory block is identified. Configuration values are serially loaded into the shifter circuit, wherein the configuration values are selected in response to the address of the defective memory block.

Abstract: A method of estimating a capacitance of each resource in a programmable logic device (PLD) is described. The current drawn by a reference circuit implemented in the PLD is measured at a given frequency and operating voltage. The capacitance of the reference circuit is calculated using the current drawn, the frequency, and the operating voltage. The current drawn by a resource load coupled to the reference circuit is measured at the given frequency and operating voltage. The capacitance of the resource load coupled to the reference circuit is calculated using the current drawn, the frequency, and the operating voltage. The capacitance of the resource load may be calculated by subtracting the capacitance of the reference circuit from the capacitance of the resource load coupled to the reference circuit.

Abstract: A memory system includes a plurality of memory modules, each including at least one memory array. Each memory array has an associated line of sense amplifier latches, wherein each line of sense amplifier latches is activated independently. Each line of sense amplifier latches is capable of caching a row of data from the associated memory array. The capacity of each memory array and the number of memory arrays are selected such that a cache hit rate of over 90 percent is achieved for the memory system.

Abstract: A semi-conductor memory device having a wide write data bandwidth is provided with high speed read-write circuitry having data amplifiers that are activated to accelerate amplification of write data signals being driven by write data drivers onto data lines of the cell array of the device during memory write cycles, as well as activated to amplify read data signals on the data lines during memory read cycles. Moreover, the data amplifiers are activatedin a self-timed manner. In one embodiment, the device is further provided with a read data buffer that is constituted with a regenerative latch and an input stage, and a write data buffer having multiple entries. The input stage of the read data buffer isolates or couples the regenerative latch to the data lines depending on whether the data lines are in a pre-charged state or not.

Abstract: An automated terrain awareness and avoidance system includes a transmitter located in a region to be protected from controlled flight into terrain accidents. The transmitter transmits an identification value to an aircraft. In response, a safety checking routine on the aircraft identifies a danger zone around the transmitter, and determines whether the aircraft has (or will) enter the danger zone. If the safety checking routine determines that the aircraft has (or will) enter the danger zone, the safety checking routine determines a safe route and engages the autopilot, which steers the aircraft along the safe route. The safety checking routine also causes a password to be transmitted to an air route traffic control center (ARTCC). The autopilot is disengaged if the safety checking routine determines the aircraft is no longer on course to enter the danger zone, or when the password, which must be received from the ARTCC, is entered.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles.

Abstract: A self-aligned process for fabricating a non-volatile memory cell having two isolated floating gates. The process includes forming a gate dielectric layer over a semiconductor substrate. A floating gate layer is then formed over the gate dielectric layer. A disposable layer is formed over the floating gate layer, and patterned to form a disposable mask having a minimum line width. Sidewall spacers are formed adjacent to the disposable mask, and source/drain regions are implanted in the substrate, using the disposable mask and the sidewall spacers as an implant mask. The disposable mask is then removed, and the floating gate layer is etched through the sidewall spacers, thereby forming a pair of floating gate regions. The sidewall spacers are removed, and an oxidation step is performed, thereby forming an oxide region that surrounds the floating gate regions. A control gate is then formed over the oxide region.

Abstract: A pressure sensor having a flexible membrane which is moved by an external force, such as pressure from an air flow. The flexible membrane extends over a semiconductor frame having an opening, such that a portion of the flexible membrane extends over the semiconductor frame, and a portion of the flexible membrane extends over the opening. An inherent tensile stress is present in the membrane. One or more strain gage resistors are formed on the portion of the membrane which extends over the opening of the semiconductor frame. The membrane deforms in response to an externally applied pressure. As the membrane deforms, the strain gage resistors elongate, thereby increasing the resistances of these resistors. This change in resistance is measured and used to determine the magnitude of the external pressure. In one embodiment, a Wheatstone bridge circuit is used to translate the change in resistance of the strain gage resistors into a differential voltage.

Abstract: A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried source region is formed in the substrate, wherein the top/bottom interfaces of the buried source region are located above/below the bottom of the isolation region, respectively. A recessed region is etched into the isolation region, thereby exposing sidewalls of the semiconductor island, which extend below the top interface of the buried source region. A gate dielectric is formed over the exposed sidewalls, and a gate electrode is formed in the recessed region, over the gate dielectric. A drain region is formed at the upper surface of the semiconductor island region, thereby forming a floating body region between the drain region and the buried source region. Dielectric spacers are formed adjacent to the gate electrode, thereby covering exposed edges of the gate dielectric.

Abstract: A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.

Abstract: An inductive amplifier having a feed forward boost is provided, thereby improving the gain of the inductive amplifier at frequencies greater than 1 GigaHertz. The inductive amplifier includes a feed-forward boost circuit coupled to intermediate nodes of an inductive amplifier circuit, whereby the feed-forward boost circuit generates boost currents that are added to the currents of the inductive amplifier circuit. In one embodiment, the feed-forward boost circuit includes a boost current supply, a first boost transistor coupled between the current supply and a first intermediate node of the inductive amplifier circuit, and a second boost transistor coupled between the current supply and a second intermediate node of the inductive amplifier circuit. In one embodiment, the first and second boost transistors and the inductive amplifier circuit are controlled by the same differential input signals.

Abstract: An anti-reflective layer is formed on the sidewalls of metal interconnects in an integrated circuit containing photodetector devices. After fabricating the photodetector devices, the metal interconnects are formed. An anti-reflective layer is formed over the interconnects and is directionally etched so that a portion of the anti-reflective layer remains covering the interconnect sidewalls, thereby reducing optical cross-talk in the photodetector devices due to sidewall reflection.