Abstract: In an integrated circuit having an on-chip power supply, a voltage maintenance circuit includes a decoupling capacitor connected between the output node and ground, a supplementary capacitor connected between a supplementary node and ground and a controllable transistor connected between the two capacitor nodes, so that when the output voltage drops below a threshold a reference circuit turns on the controllable transistor, thereby supplying extra charge to the output node and restoring it to its design voltage more quickly than the power supply could.

Abstract: MRAM cells are placed in the upper regions (BEOL) of an integrated circuit while simultaneously maintaining the dimensions needed for good MRAM performance and also for good operation of the logic circuit by setting the standard vertical dimension of the BEOL at the value that is suitable for logic circuits. In the areas where MRAM cells are to be placed, the (N+1)th level is etched separately. A standard etch is applied in logic areas and a deeper etch is applied in MRAM areas, so that the interlevel distance in the logic areas is the standard amount and the interlevel distance is MRAM areas is a lesser amount that is appropriate to accommodate the vertical dimensions of the material layers that go into the MRAM cells.

Abstract: In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.

Abstract: A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wordline and the transistor electrode and using the wordline as an etch stop to protect the transistor gate during the patterning of the wordlines.

Abstract: A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the hardmask layer; the portion of the circuit that has the correct gate length is covered with a blocking mask and the hardmask in the remainder is wet-etched to reduce its dimension, after which the gate stack is etched using both gate lengths of hardmask to produce different gate lengths in different areas.

Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

Abstract: A stencil-scattering mask for e-beam lithography includes four complementary sub-field reticles, each of which is exposed with one fourth of the total dose. “Doughnut” stencil shapes have four different patterns of struts, so that an area that is blocked by a strut in one shape is exposed in three other shapes.

Abstract: Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.

Abstract: Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device to substrate capacitance.

Abstract: An e-beam lithographic system capable of in situ registration. The system has an optics section such as a VAIL lens. A controllable stage moves a substrate with respect to the beam axis to place substrate writing fields beneath the beam. A field locking target between the optics section and the stage has an aperture sized to permit the beam to write a target field on the substrate. The field locking target includes alignment or registration marks around the aperture. A differential interferometric system measures the relative positions of the field locking target and the stage and controls stage position. The beam patterns the substrate on a field by field basis. As the stage is moving into position for each field, the beam is swept until it hits the alignment marks, thereby checking system alignment. The beam control data, i.e., coil currents necessary to hit the marks are stored, and drift correction values calculated from the beam control data.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.

Abstract: Transistors having self-aligned dielectric layers under the source/drain contacts are formed by constructing transistors up to the LDD implant; etching STI oxide selective to Si and nitride to form a self-aligned contact recess; depositing an insulating layer in the bottom of the contact recess; recessing the insulating layer to leave room for a conductive contact layer; depositing the contact layer to make contact on a vertical surface to the Si underneath the gate sidewalls; recessing the contact layer; forming interlayer dielectric and interconnect to complete the circuit.

Abstract: A method and structure for manufacturing an integrated circuit chip includes a substrate and an opening in the substrate. The opening has at least one step and a first conductor in the opening below the step. The invention has a first diffusion region in the substrate adjacent the first conductor and below the step. A gate conductor is over the step and in the opening. A second conductor is over the substrate adjacent the gate conductor. A second diffusion region in the substrate is adjacent the second comductor.

Abstract: A memory decoder system is disclosed. In an exemplary embodiment of the invention, the system includes a matrix of memory cells, arranged into rows and columns, with a plurality of wordline drivers corresponding to each row in the matrix. A group of wordline driver-decoder blocks each contains a subset of the plurality of wordline drivers therein, with each of the wordline driver-decoder blocks being separated by a row control block. The row control block includes control circuitry for the wordline drivers. For any given wordline driver-decoder block, a first group of wordline drivers contained therein is controlled by a row control block located on one side of the given wordline driver-decoder block, while a second group of wordline drivers contained therein is controlled by a row control block located on an opposite side of the given wordline driver-decoder block.

Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.

Abstract: A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.

Abstract: Device for cancelling the effects of the reflection in a signal transmission system (10) including a driver (12) and a plurality of n receivers (14, 16) wherein signals are sent according to a multipoint topology from the driver to the receivers, each receiver having an internal capacitance and sending back reflection signals to the driver each time a signal is transmitted thereto by the driver. The device comprises circuit means causing the signal resulting from the sequential reflections due to a given receiver and then due to the driver to have the same magnitude but the reverse sign as the sum of all signals received in the given receiver resulting from the reflections due to all receivers, and the net linking the driver to each receiver comprises delay means (40) enabling the propagating time of a signal sent from the driver to this receiver to be identical for each receiver, whereby the total sum of all reflection signals arriving in the given receiver at the same time is equal to zero.

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

Abstract: A scattering target for use in a particle beam system is formed from a grid of gold on a substrate of carbon, with an intermediate smoothing layer (e.g. copper) on the carbon to provide a surface sufficiently smooth to provide an adequate target. An optional bonding layer may be used to improve adhesion between the gold and the smoothing layer.