Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable “blowing” of the fuse in the fuse region underlying the filler material. Since the “blow” area is predictable, damage to adjacent structures can be minimized or eliminated.

Abstract: A method, and a system for employing the method, for compacting the amount of memory required to store a two dimensional array of exposure spot shapes in a numerically controlled (NC) electron beam lithography tool. The method includes the steps of: sorting the shapes in a selected line based on the widths and heights of the shapes; identifying and removing from contention a group of shapes in the selected line having common widths and heights; determining a dosage requirement for the shapes in the group; and applying one or more commands based on the group and the determined dosed requirement to enable the NC electron beam lithography tool to draw the two dimensional array of exposure spot shapes.

Abstract: In a bulk silicon process, an insulating layer is placed under the portion of the source and drain used for contacts, thereby reducing junction capacitance. The processing involves a smaller than usual transistor area that is not large enough to hold the contacts, which are placed in an aperture cut into the shallow trench isolation.

Abstract: In an SOI integrated circuit employing shallow trench isolation, the walls of the transistor active area have a nitridized oxide layer grown on them, thereby preventing the diffusion of dopants out of the transistor body and preventing a shift in threshold voltage.

Abstract: A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

Abstract: A method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around the trenches. The straps and trench sidewalls are doped to form a resistive connection. During a subsequent shallow trench isolation (STI) process, which involves an oxidation step, the exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate.

Abstract: A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

Abstract: A test structure and method for determining DRAM cell leakage. The cell leakage test structure includes a pair of buried strap test structures. Each buried strap test structure includes multiple trench capacitors formed in a silicon body. Each trench capacitor is connected to a trench sidewall diffusion by at least one buried strap. An n-well ring surrounds each buried strap test structure and divides the buried strap test structure into two separate array p-wells, one being a contact area and the other a leakage test area. The contact area includes contacts to the trench capacitor plates for the corresponding buried strap test structure. In one buried strap test structure, a layer of polysilicon, essentially covers the trench capacitors in the leakage test area to block source/drain region formation there. The other of the two buried strap test structures includes polysilicon lines simulating wordlines with source and drain regions form on either side.

Abstract: A dual-gate SOI transistor that has the back gate self-aligned to the front gate is formed on an SOI substrate by forming a conventional gate stack having an etch resistant layer on the top; growing epitaxial silicon on the upper surface of the silicon device layer, which leaves apertures on both sides of the gate stack; filling the apertures with etch resistant spacers; defining an etch window bracketing the gate stack and etching alignment trenches down to the bulk silicon. A shallow layer of etch resistant aligning material is deposited on the bottom of the alignment trenches, after which the conventional back end processing as followed of deposition of a supporting layer that supports the layers of the circuit during later processing. The bulk silicon is removed and the back side is patterned to expose the buried oxide below the transistors; an oxide etch leaves a self-aligned backside aperture below the transistors, defined by the etch resistant aligning material.

Abstract: A resistive heater element is integrally formed with a beam shaping aperture foil by lithographic patterning of a doped semiconductor layer of which the aperture foil is formed over an insulator, resulting in a device of greatly increased structural robustness and reliability. Heat provided to the aperture foil by the heater element greatly reduces the accretion of deposits thereon which can distort the aperture shape and/or, deflect the beam when electrostatic charge accumulates thereon. The lithographic patterning process for fabricating the integral heater and aperture foil is only slightly increased in complexity from the current process for fabricating an aperture foil alone by an additional resist application and exposure, ohmic contact formation and use of an additional etchant and is of high yield.

Abstract: A DRAM memory cell having a trench capacitor includes a vertical pass transistor formed in the top of the trench in a process that forms a doped poly protective layer on the upper sidewalls above a sacrificial intrinsic poly spacer layer, the doped poly protecting the sidewalls while the intrinsic poly spacer layer is removed and replaced with a conductive strap layer that both forms a strap from the capacitor electrode and serves as a source of dopant to form a transistor electrode in the silicon substrate; the protective layer and the upper portion of the strap material being removed simultaneously so that no extra step is required; after which the trench walls are oxidized to form the transistor gate dielectric and conductive material is deposited to form the wordline and the gates for the vertical transistors simultaneously.

Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators P-wells, wherein the first divots have a greater depth than the second divots.

Abstract: A power management system for integrated circuits having several voltage levels shorts two buses together during a voltage ramp period, so that the charge pumps connected to both buses drive both buses. When the lower bus reaches its design voltage, the shorting switch is opened and a set of pumps drives the higher bus to its design voltage. After the ramp, the voltage controls on the pumps and the current path to a bus are switched as needed in order to supply each bus with the required current capacity.

Abstract: Disclosed is a method comprising providing a silicon surface with an underlying insulator layer, providing a plurality of gates adjacent to source/drain regions, growing source/drains between the said gates such that the source/drains are thicker in regions of larger gate-to-gate pitch, and doping the source/drains with one or more dopants such that the dopants abut the underlying insulator layer.

Abstract: A conventional initial deep trench structure consists of a patterned Si3N4 pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO2 collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO2 is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO2 is etched at least 6 times faster than the Si3N4 (stopping on the Si3N4 pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6× the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages.

Abstract: Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.

Abstract: A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.

Abstract: A method of calibrating an electron beam system in which a plurality of standard grids are mounted in various presentations in the electron beam system and treated as different presentations of the same grid for the purposes of applying algorithms to adjust a computer-controlled system for deflecting the electron beam. A standard grid mask is fabricated in an electron beam system and used in a stepper to make the standard grids, the same stepper and the same stepper optics being used to make each of the standard grids.

Abstract: An electrostatic chuck has its electrodes biased with respect to the self-bias potential induced by the plasma on the wafer, thereby providing improved resistance to breakdown in spite of variation of the wafer potential during processing. An alternate embodiment further suppresses the formation of vacuum arcs between the back of the wafer being processed and the body of the chuck by the interposition of a conductive guard ring at the self-bias potential, thereby defining an equipotential area between the closest electrode and the wafer.

Abstract: An electrostatic chuck is disclosed that is resistant to the formation of vacuum arcs between the back of the wafer being processed and the body of the chuck. A guard ring surrounds the chuck and floats close to the self-bias potential induced by the plasma on the wafer. The voltage between the wafer and the closest electrode is thereby capacitively divided by the guard ring.